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Now compiles, dunno if it works...

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This commit is contained in:
xolatile
2024-07-24 15:31:02 -04:00
parent dd5be337a6
commit 3de231c317
4 changed files with 18 additions and 197 deletions
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39
source/assembler.c
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@ -7,9 +7,9 @@
#define IRREGULAR_BEGIN (INC)
#define IRREGULAR_END (IDIV)
#define SPECIAL_1_BEGIN (NOP)
#define SPECIAL_1_END (STOSD)
#define SPECIAL_2_BEGIN (SYSENTER)
#define SPECIAL_2_END (XLATB)
#define SPECIAL_1_END (PUSHF)
#define SPECIAL_2_BEGIN (SYSCALL)
#define SPECIAL_2_END (FCOS)
#define JUMP_IF_BEGIN (JO)
#define JUMP_IF_END (JG)
#define MOVE_IF_BEGIN (CMOVO)
@ -92,8 +92,8 @@ static void short_prefix (unsigned int size) {
}
static void long_prefix (unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
int to_upper = (to == REG) && (upper (destination));
int from_upper = (to == REG) && (upper (destination));
int to_upper = (to == REG) && (upper (destination));
int from_upper = (from == REG) && (upper (source));
input ((size == D64) || (to_upper) || (from_upper), 0x40 + 0x01 * to_upper + 0x04 * from_upper + 0x08 * (size == D64));
}
@ -106,10 +106,6 @@ static void modify_memory (unsigned int operation, unsigned int to, unsigned int
input (((to == MEM) && (from == REG)) || ((to == REG) && (from == MEM)), 0x05 + 0x08 * operation * ((to == MEM) && (from == IMM)));
}
static void modify_register_0 (unsigned int size) {
input (! ((to == REG) && (destination == 0)) && (from == IMM), 0x80 + 0x01 * (size != D8));
}
static void build_regular (unsigned int operation, unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
short_prefix (size);
@ -124,8 +120,6 @@ static void build_regular (unsigned int operation, unsigned int size, unsigned i
input ((from == IMM) && (to == REG) && (destination == 0), 0x05 + 0x08 * (operation & 0x07) - 0x01 * (size == D8));
modify_register_0 (size);
input (! ((from == IMM) && (to == REG) && (destination == 0)),
(destination & 0x07) * ((to == REG) && (from == IMM))
+ 0x08 * (operation - REGULAR_BEGIN)
@ -138,8 +132,8 @@ static void build_regular (unsigned int operation, unsigned int size, unsigned i
modify_registers (to, destination, from, source);
modify_memory ((to == REG) && (from == MEM), destination);
modify_memory ((to == MEM) && (from == REG), source);
modify_memory (destination, to, from);
modify_memory (source, to, from);
input_by ((to == REG) && (from == MEM), D32, ~0x0u);
input_by ((to == REG) && (from == IMM), size, source);
@ -163,8 +157,7 @@ static void build_irregular (unsigned int operation, unsigned int size, unsigned
static void build_special_1 (unsigned int operation) {
const unsigned char data [] = {
0x90, 0xc3, 0xcb, 0xc9, 0xf0, 0xf4, 0x9d, 0x9c, 0x9b, 0xf8, 0xfc, 0xfa, 0xf9, 0xfd, 0xfb, 0xf5, 0x6c, 0x6d, 0x6e, 0x6f, 0x99, 0x98, 0xec, 0xed, 0xcc, 0xcf, 0xac,
0xad, 0xee, 0xef, 0xae, 0xaf, 0xaa, 0xab
0x90, 0xc3, 0xcb, 0xc9, 0x9d, 0x9c
};
input (1, data [operation - SPECIAL_1_BEGIN]);
@ -172,9 +165,10 @@ static void build_special_1 (unsigned int operation) {
static void build_special_2 (unsigned int operation) {
const unsigned short data [] = {
0x340f, 0x350f, 0x050f, 0x070f, 0x90f3, 0xa20f, 0x770f, 0xaa0f, 0xd0d9, 0xe0d9, 0xe1d9, 0xe4d9, 0xe5d9, 0xe8d9, 0xe9d9, 0xead9, 0xebd9, 0xecd9, 0xedd9, 0xeed9,
0xf0d9, 0xf1d9, 0xf2d9, 0xf3d9, 0xf4d9, 0xf5d9, 0xf6d9, 0xf7d9, 0xf8d9, 0xf9d9, 0xfad9, 0xfbd9, 0xfcd9, 0xfdd9, 0xfed9, 0xffd9, 0x6d66, 0x6f66, 0x9966, 0x9948,
0x9866, 0x9848, 0x080f, 0x090f, 0x0b0f, 0x060f, 0xed66, 0xcf48, 0xad66, 0xad48, 0xef66, 0x330f, 0x320f, 0x310f, 0xaf66, 0xaf48, 0xab66, 0xab48, 0x300f, 0xd748
0x050f, 0xa20f, 0xd0d9, 0xe0d9, 0xe1d9, 0xe4d9, 0xe5d9, 0xe8d9,
0xe9d9, 0xead9, 0xebd9, 0xecd9, 0xedd9, 0xeed9, 0xf0d9, 0xf1d9,
0xf2d9, 0xf3d9, 0xf4d9, 0xf5d9, 0xf6d9, 0xf7d9, 0xf8d9, 0xf9d9,
0xfad9, 0xfbd9, 0xfcd9, 0xfdd9, 0xfed9, 0xffd9
};
input_by (1, D16, data [operation - SPECIAL_2_BEGIN]);
@ -198,7 +192,7 @@ static void build_move_if (unsigned int operation, unsigned int size, unsigned i
input (1, 0x40 + operation - MOVE_IF_BEGIN);
modify_registers (to, destination, from, source);
modify_memory ((to == REG) && (from == MEM), destination);
modify_memory (destination, to, from);
}
static void build_jump (unsigned int size, unsigned int to, unsigned int destination) {
@ -223,8 +217,8 @@ static void build_move (unsigned int size, unsigned int to, unsigned int destina
input ((to == REG) && (from == MEM), 0x8a + 0x01 * (size != D8));
input ((to == MEM) && (from == REG), 0x88 + 0x01 * (size != D8));
modify_memory ((to == REG) && (from == MEM), destination);
modify_memory ((to == MEM) && (from == REG), source);
modify_memory (destination, to, from);
modify_memory (source, to, from);
modify_registers (to, destination, from, source);
@ -298,7 +292,8 @@ static void build_push (unsigned int size, unsigned int from, unsigned int sourc
static void build_float (unsigned int operation, unsigned int size, unsigned int from, unsigned int source) {
input (from == MEM, 0xd8 + 0x04 * (size == D64));
modify_memory (from == MEM, operation);
modify_memory (operation, 0, from);
input_at (from == MEM, size, source, 0);
}

58
source/eaxhla.l
View File

@ -155,22 +155,10 @@ nop { return INOP; }
adc { return ITADC; }
add { return ITADD; }
and { return ITAND; }
cbw { return ITCBW; }
cdq { return ITCDQ; }
cdqe { return ITCDQE; }
clc { return ITCLC; }
cld { return ITCLD; }
cli { return ITCLI; }
clts { return ITCLTS; }
cmc { return ITCMC; }
cmp { return ITCMP; }
cpuid { return ITCPUID; }
cqo { return ITCQO; }
cwd { return ITCWD; }
cwde { return ITCWDE; }
dec { return ITDEC; }
div { return ITDIV; }
emms { return ITEMMS; }
f2xm1 { return ITF2XM1; }
fabs { return ITFABS; }
fchs { return ITFCHS; }
@ -199,74 +187,28 @@ fxam { return ITFXAM; }
fxtract { return ITFXTRACT; }
fyl2x { return ITFYL2X; }
fyl2xp1 { return ITFYL2XP1; }
hlt { return ITHLT; }
idiv { return ITIDIV; }
imul { return ITIMUL; }
inal { return ITINAL; }
inax { return ITINAX; }
inc { return ITINC; }
ineax { return ITINEAX; }
insb { return ITINSB; }
insd { return ITINSD; }
insw { return ITINSW; }
int3 { return ITINT3; }
invd { return ITINVD; }
iretd { return ITIRETD; }
iretq { return ITIRETQ; }
je { return ITJE; }
jmp { return ITJMP; }
jne { return ITJNE; }
leave { return ITLEAVE; }
lock { return ITLOCK; }
lodsb { return ITLODSB; }
lodsd { return ITLODSD; }
lodsq { return ITLODSQ; }
lodsw { return ITLODSW; }
mov { return ITMOV; }
mul { return ITMUL; }
neg { return ITNEG; }
nop { return ITNOP; }
not { return ITNOT; }
or { return ITOR; }
outal { return ITOUTAL; }
outax { return ITOUTAX; }
outeax { return ITOUTEAX; }
outsb { return ITOUTSB; }
outsd { return ITOUTSD; }
outsw { return ITOUTSW; }
pause { return ITPAUSE; }
pop { return ITPOP; }
popf { return ITPOPF; }
pushf { return ITPUSHF; }
rdmsr { return ITRDMSR; }
rdpmc { return ITRDPMC; }
rdtsc { return ITRDTSC; }
retf { return ITRETF; }
retn { return ITRETN; }
rsm { return ITRSM; }
sar { return ITSAR; }
sbb { return ITSBB; }
scasb { return ITSCASB; }
scasd { return ITSCASD; }
scasq { return ITSCASQ; }
scasw { return ITSCASW; }
stc { return ITSTC; }
std { return ITSTD; }
sti { return ITSTI; }
stosb { return ITSTOSB; }
stosd { return ITSTOSD; }
stosq { return ITSTOSQ; }
stosw { return ITSTOSW; }
sub { return ITSUB; }
syscall { return ITSYSCALL; }
sysenter { return ITSYSENTER; }
sysexit { return ITSYSEXIT; }
sysret { return ITSYSRET; }
ud2 { return ITUD2; }
wait { return ITWAIT; }
wbinvd { return ITWBINVD; }
wrmsr { return ITWRMSR; }
xlatb { return ITXLATB; }
xor { return ITXOR; }
/* #placeholder<instruction_scanner_instructions> END

60
source/eaxhla.y
View File

@ -93,7 +93,7 @@
// Instructions
%token INOP
// #placeholder<instruction_token_list> BEGIN
%token ITADC ITADD ITAND ITCBW ITCDQ ITCDQE ITCLC ITCLD ITCLI ITCLTS ITCMC ITCMP ITCPUID ITCQO ITCWD ITCWDE ITDEC ITDIV ITEMMS ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITHLT ITIDIV ITIMUL ITINAL ITINAX ITINC ITINEAX ITINSB ITINSD ITINSW ITINT3 ITINVD ITIRETD ITIRETQ ITJE ITJMP ITJNE ITLEAVE ITLOCK ITLODSB ITLODSD ITLODSQ ITLODSW ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITOUTAL ITOUTAX ITOUTEAX ITOUTSB ITOUTSD ITOUTSW ITPAUSE ITPOP ITPOPF ITPUSHF ITRDMSR ITRDPMC ITRDTSC ITRETF ITRETN ITRSM ITSAR ITSBB ITSCASB ITSCASD ITSCASQ ITSCASW ITSTC ITSTD ITSTI ITSTOSB ITSTOSD ITSTOSQ ITSTOSW ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITUD2 ITWAIT ITWBINVD ITWRMSR ITXLATB ITXOR
%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSHF ITRETF ITRETN ITSAR ITSBB ITSUB ITSYSCALL ITXOR
// #placeholder<instruction_token_list> END
// Instruction-likes
@ -427,44 +427,10 @@ instruction: INOP { append_instructions(NOP); }
| ITRETN { append_instructions(RETN); }
| ITRETF { append_instructions(RETF); }
| ITLEAVE { append_instructions(LEAVE); }
| ITLOCK { append_instructions(LOCK); }
| ITHLT { append_instructions(HLT); }
| ITPOPF { append_instructions(POPF); }
| ITPUSHF { append_instructions(PUSHF); }
| ITWAIT { append_instructions(WAIT); }
| ITCLC { append_instructions(CLC); }
| ITCLD { append_instructions(CLD); }
| ITCLI { append_instructions(CLI); }
| ITSTC { append_instructions(STC); }
| ITSTD { append_instructions(STD); }
| ITSTI { append_instructions(STI); }
| ITCMC { append_instructions(CMC); }
| ITINSB { append_instructions(INSB); }
| ITINSD { append_instructions(INSD); }
| ITOUTSB { append_instructions(OUTSB); }
| ITOUTSD { append_instructions(OUTSD); }
| ITCDQ { append_instructions(CDQ); }
| ITCWDE { append_instructions(CWDE); }
| ITINAL { append_instructions(INAL); }
| ITINEAX { append_instructions(INEAX); }
| ITINT3 { append_instructions(INT3); }
| ITIRETD { append_instructions(IRETD); }
| ITLODSB { append_instructions(LODSB); }
| ITLODSD { append_instructions(LODSD); }
| ITOUTAL { append_instructions(OUTAL); }
| ITOUTEAX { append_instructions(OUTEAX); }
| ITSCASB { append_instructions(SCASB); }
| ITSCASD { append_instructions(SCASD); }
| ITSTOSB { append_instructions(STOSB); }
| ITSTOSD { append_instructions(STOSD); }
| ITSYSENTER { append_instructions(SYSENTER); }
| ITSYSEXIT { append_instructions(SYSEXIT); }
| ITSYSCALL { append_instructions(SYSCALL); }
| ITSYSRET { append_instructions(SYSRET); }
| ITPAUSE { append_instructions(PAUSE); }
| ITCPUID { append_instructions(CPUID); }
| ITEMMS { append_instructions(EMMS); }
| ITRSM { append_instructions(RSM); }
| ITFNOP { append_instructions(FNOP); }
| ITFCHS { append_instructions(FCHS); }
| ITFABS { append_instructions(FABS); }
@ -493,30 +459,6 @@ instruction: INOP { append_instructions(NOP); }
| ITFSCALE { append_instructions(FSCALE); }
| ITFSIN { append_instructions(FSIN); }
| ITFCOS { append_instructions(FCOS); }
| ITINSW { append_instructions(INSW); }
| ITOUTSW { append_instructions(OUTSW); }
| ITCWD { append_instructions(CWD); }
| ITCQO { append_instructions(CQO); }
| ITCBW { append_instructions(CBW); }
| ITCDQE { append_instructions(CDQE); }
| ITINVD { append_instructions(INVD); }
| ITWBINVD { append_instructions(WBINVD); }
| ITUD2 { append_instructions(UD2); }
| ITCLTS { append_instructions(CLTS); }
| ITINAX { append_instructions(INAX); }
| ITIRETQ { append_instructions(IRETQ); }
| ITLODSW { append_instructions(LODSW); }
| ITLODSQ { append_instructions(LODSQ); }
| ITOUTAX { append_instructions(OUTAX); }
| ITRDPMC { append_instructions(RDPMC); }
| ITRDMSR { append_instructions(RDMSR); }
| ITRDTSC { append_instructions(RDTSC); }
| ITSCASW { append_instructions(SCASW); }
| ITSCASQ { append_instructions(SCASQ); }
| ITSTOSW { append_instructions(STOSW); }
| ITSTOSQ { append_instructions(STOSQ); }
| ITWRMSR { append_instructions(WRMSR); }
| ITXLATB { append_instructions(XLATB); }
| ITJMP relative { append_instructions( JMP, D32, REL, $2 ); }
| ITJE relative { append_instructions( JE, D32, REL, $2 ); }
| ITJNE relative { append_instructions( JNE, D32, REL, $2 ); }

58
tool/generators/instructions.tcl
View File

@ -3,44 +3,10 @@ set instructions {
{retn}
{retf}
{leave}
{lock}
{hlt}
{popf}
{pushf}
{wait}
{clc}
{cld}
{cli}
{stc}
{std}
{sti}
{cmc}
{insb}
{insd}
{outsb}
{outsd}
{cdq}
{cwde}
{inal}
{ineax}
{int3}
{iretd}
{lodsb}
{lodsd}
{outal}
{outeax}
{scasb}
{scasd}
{stosb}
{stosd}
{sysenter}
{sysexit}
{syscall}
{sysret}
{pause}
{cpuid}
{emms}
{rsm}
{fnop}
{fchs}
{fabs}
@ -69,30 +35,6 @@ set instructions {
{fscale}
{fsin}
{fcos}
{insw}
{outsw}
{cwd}
{cqo}
{cbw}
{cdqe}
{invd}
{wbinvd}
{ud2}
{clts}
{inax}
{iretq}
{lodsw}
{lodsq}
{outax}
{rdpmc}
{rdmsr}
{rdtsc}
{scasw}
{scasq}
{stosw}
{stosq}
{wrmsr}
{xlatb}
{jmp relative}
{je relative}
{jne relative}