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Added shifting instructions, fixed move, negatives, and more...

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This commit is contained in:
xolatile 2024-07-28 18:28:22 -04:00
parent 08ab8e887b
commit 4eede012f0
7 changed files with 112 additions and 24 deletions
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49
source/assembler.c
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@ -16,6 +16,8 @@
#define MOVE_IF_END (CMOVG)
#define FLOAT_BEGIN (FADD)
#define FLOAT_END (FDIVR)
#define SHIFTER_BEGIN (ROL)
#define SHIFTER_END (SAR)
static int assemble_clean_up_queued = 0;
@ -270,7 +272,8 @@ static unsigned int build_move (unsigned int * array) {
to = array [2],
destination = array [3],
from = array [4],
source = array [5];
source = array [5],
extension = array [6];
short_prefix (size);
@ -285,21 +288,23 @@ static unsigned int build_move (unsigned int * array) {
modify_registers (to, destination, from, source);
inset ((to == REG) && ((from == IMM) || (from == REL)), 0xb8 + 0x01 * (destination & 0x07));
inset ((to == REG) && ((from == IMM) || (from == REL)), 0xb0 + 0x08 * (size != D8) + 0x01 * (destination & 0x07));
inset ((to == MEM) && (from == IMM), 0xc6 + 0x01 * (size != D8));
inset ((to == MEM) && (from == IMM), 0x05);
inset_memory ((to == REG) && (from == MEM), D32, source, 0x1000 - (text_sector_size + 4));
inset_immediate ((to == REG) && (from == IMM), size, source);
inset_memory ((to == MEM) && (from == REG), D32, destination, 0x1000 - (text_sector_size + 4));
inset_memory ((to == MEM) && (from == IMM), D32, destination, 0x1000 - (text_sector_size + 4));
inset_immediate ((to == MEM) && (from == IMM), size, source);
inset_memory ((to == REG) && (from == REL), D32, source, 0x4010b0);
inset_memory ((to == REG) && (from == MEM), D32, source, 0x1000 - (text_sector_size + 4));
inset_memory ((to == MEM) && (from == REG), D32, destination, 0x1000 - (text_sector_size + 4));
inset_memory ((to == MEM) && (from == IMM), D32, destination, 0x1000 - (text_sector_size + 4));
inset_memory ((to == REG) && (from == REL), D32, source, 0x4010b0);
inset_immediate ((to == REG) && (from == IMM) && (size == D64), D32, 0);
inset_immediate ((to == REG) && (from == IMM) && (size != D64), size, source);
inset_immediate ((to == MEM) && (from == IMM) && (size != D64), size, source);
inset_immediate ((to == REG) && (from == IMM) && (size == D64), D32, source);
inset_immediate ((to == REG) && (from == IMM) && (size == D64), D32, extension);
inset_immediate ((to == REG) && (from == IMM) && (size == D64), D32, 0);
return (5);
return (5 + (size == D64));
}
static unsigned int build_call (unsigned int * array) {
@ -345,6 +350,28 @@ static unsigned int build_float (unsigned int * array) {
return (3);
}
static unsigned int build_shifter (unsigned int * array) {
unsigned int operation = array [0],
size = array [1],
to = array [2],
destination = array [3],
offset = array [5];
short_prefix (size);
long_prefix (size, to, destination, 0, 0);
inset (1, 0xc0 + 0x01 * (size != D8));
inset (to == REG, 0x05 + 0x08 * (operation & 7));
inset (to == MEM, 0xc0 + 0x08 * (operation & 7));
inset_memory (to == MEM, D32, destination, 0x1000 - (text_sector_size + 4));
inset_immediate (1, D8, offset);
return (5);
}
static unsigned int build_in_out (unsigned int * array) {
unsigned int move = array [0],
size = array [1],
@ -451,6 +478,8 @@ int assemble (unsigned int count, unsigned int * array) {
index += build_move_if (& array [index]);
} else if ((array [index] >= FLOAT_BEGIN) && (array [index] <= FLOAT_END)) {
index += build_float (& array [index]);
} else if ((array [index] >= SHIFTER_BEGIN) && (array [index] <= SHIFTER_END)) {
index += build_shifter (& array [index]);
} else if ((array [index] == IN) || (array [index] == OUT)) {
index += build_in_out (& array [index]);
} else switch (array [index]) {

24
source/assembler.h
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@ -1,6 +1,28 @@
#ifndef ASSEMBLER_H
#define ASSEMBLER_H
#define JNPE JPO
#define JNPO JPE
#define JNB JAE
#define JNBE JA
#define JNA JBE
#define JNAE JB
#define JNL JGE
#define JNLE JG
#define JNG JLE
#define JNGE JL
#define CMOVNPE CMOVPO
#define CMOVNPO CMOVPE
#define CMOVNB CMOVAE
#define CMOVNBE CMOVA
#define CMOVNA CMOVBE
#define CMOVNAE CMOVB
#define CMOVNL CMOVGE
#define CMOVNLE CMOVG
#define CMOVNG CMOVLE
#define CMOVNGE CMOVL
enum {
D8, D16, D32, D64
};
@ -14,6 +36,7 @@ enum {
ADD, OR, ADC, SBB, AND, SUB, XOR, CMP,
INC, DEC, NOT, NEG, MUL, IMUL, DIV, IDIV,
FADD, FMUL, FCOM, FCOMP, FSUB, FSUBR, FDIV, FDIVR,
ROL, ROR, RCL, RCR, SAL, SHR, SHL, SAR,
NOP, RETN, RETF, LEAVE, POPF, PUSHF,
SYSCALL, CPUID, FNOP, FCHS, FABS, FTST, FXAM, FLD1,
FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, FLDZ, F2XM1, FYL2X,
@ -25,7 +48,6 @@ enum {
CMOVO, CMOVNO, CMOVB, CMOVAE, CMOVE, CMOVNE, CMOVBE, CMOVA,
CMOVS, CMOVNS, CMOVPE, CMOVPO, CMOVL, CMOVGE, CMOVLE, CMOVG,
BSWAP, TEST, XCHG, LEA, BSF, BSR,
RCL, RCR, ROL, ROR, SHL, SHR, SAL, SAR,
REP, REPE, REPNE, REPZ, REPNZ, LOOP, LOOPE, LOOPNE
};

8
source/eaxhla.l
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@ -204,9 +204,17 @@ or { return ITOR; }
pop { return ITPOP; }
popf { return ITPOPF; }
pushf { return ITPUSHF; }
rcl { return ITRCL; }
rcr { return ITRCR; }
retf { return ITRETF; }
retn { return ITRETN; }
rol { return ITROL; }
ror { return ITROR; }
sal { return ITSAL; }
sar { return ITSAR; }
sbb { return ITSBB; }
shl { return ITSHL; }
shr { return ITSHR; }
sub { return ITSUB; }
syscall { return ITSYSCALL; }
xor { return ITXOR; }

18
source/eaxhla.y
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@ -93,7 +93,7 @@
// Instructions
%token INOP
// #placeholder<instruction_token_list> BEGIN
%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSHF ITRETF ITRETN ITSBB ITSUB ITSYSCALL ITXOR
%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSHF ITRCL ITRCR ITRETF ITRETN ITROL ITROR ITSAL ITSAR ITSBB ITSHL ITSHR ITSUB ITSYSCALL ITXOR
// #placeholder<instruction_token_list> END
// Instruction-likes
@ -561,6 +561,22 @@ instruction: INOP { append_instructions(NOP); }
| ITMOV register memory { append_instructions( MOV, $2.size, REG, $2.number, MEM, $3 ); }
| ITMOV memory register { append_instructions( MOV, D32, MEM, $2, REG, $3.number ); }
| ITMOV memory immediate { append_instructions( MOV, D32, MEM, $2, $3.type, $3.value ); }
| ITROL register immediate { append_instructions( ROL, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITROR register immediate { append_instructions( ROR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITRCL register immediate { append_instructions( RCL, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITRCR register immediate { append_instructions( RCR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSAL register immediate { append_instructions( SAL, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSHR register immediate { append_instructions( SHR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSHL register immediate { append_instructions( SHL, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITROL memory immediate { append_instructions( ROL, D32, MEM, $2, $3.type, $3.value ); }
| ITROR memory immediate { append_instructions( ROR, D32, MEM, $2, $3.type, $3.value ); }
| ITRCL memory immediate { append_instructions( RCL, D32, MEM, $2, $3.type, $3.value ); }
| ITRCR memory immediate { append_instructions( RCR, D32, MEM, $2, $3.type, $3.value ); }
| ITSAL memory immediate { append_instructions( SAL, D32, MEM, $2, $3.type, $3.value ); }
| ITSHR memory immediate { append_instructions( SHR, D32, MEM, $2, $3.type, $3.value ); }
| ITSHL memory immediate { append_instructions( SHL, D32, MEM, $2, $3.type, $3.value ); }
| ITSAR memory immediate { append_instructions( SAR, D32, MEM, $2, $3.type, $3.value ); }
// #placeholder<instruction_parser_rules> END
;

2
test/heyo_world.eax
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@ -1,5 +1,5 @@
program heyo_world
s8 <12> message "Heyo world!\n" // AVAR D8 12 ...
s8 <12> message = "Heyo world!\n" // AVAR D8 12 ...
begin // DECL 0XFFFFFFFFU
mov eax 1 // MOV D32 REG R0 IMM 1

19
test/india.eax
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@ -1,15 +1,12 @@
unix program hello
s8 <> message = "Hello, world!\n"
begin
mov ebx 0
mov edi 1
mov esi message
mov edx 14
india:
mov eax 1
syscall
inc ebx
cmp ebx 3
jne india
mov al 0x11
mov ax 0x1122
mov eax 0x11223344
mov cl 0x11
mov cx 0x1122
mov ecx 0x11223344
exit 0
end program

16
tool/generators/instructions.tcl
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@ -100,6 +100,22 @@ set instructions {
{mov register memory}
{mov memory register}
{mov memory immediate}
{rol register immediate}
{ror register immediate}
{rcl register immediate}
{rcr register immediate}
{sal register immediate}
{shr register immediate}
{shl register immediate}
{sar register immediate}
{rol memory immediate}
{ror memory immediate}
{rcl memory immediate}
{rcr memory immediate}
{sal memory immediate}
{shr memory immediate}
{shl memory immediate}
{sar memory immediate}
}
proc malformed_instruction {i} {