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Added proto game of life, ASM and EAX, many more instruction combos, refacored assembler...

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This commit is contained in:
xolatile 2024-07-24 22:09:03 -04:00
parent 3de231c317
commit 630b6aa36c
6 changed files with 227 additions and 9 deletions
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11
source/assembler.c
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@ -135,11 +135,12 @@ static void build_regular (unsigned int operation, unsigned int size, unsigned i
modify_memory (destination, to, from);
modify_memory (source, to, from);
input_by ((to == REG) && (from == MEM), D32, ~0x0u);
input_at ((to == REG) && (from == MEM), D32, source, 0x1000);
input_by ((to == REG) && (from == IMM), size, source);
input_by ((to == MEM) && (from == REG), D32, ~0x0u);
input_by ((to == MEM) && (from == IMM), D32, ~0x0u);
input_at ((to == MEM) && (from == REG), D32, destination, 0x1000);
input_at ((to == MEM) && (from == IMM), D32, destination, 0x1000);
input_by ((to == MEM) && (from == IMM), size, source);
input_at ((to == REG) && (from == REL), D32, source, 0x4010b0);
}
static void build_irregular (unsigned int operation, unsigned int size, unsigned int to, unsigned int destination) {
@ -153,6 +154,8 @@ static void build_irregular (unsigned int operation, unsigned int size, unsigned
input (to == REG, 0xc0 + 0x08 * (operation - IRREGULAR_BEGIN) + 0x01 * (destination & 0x07));
input (to == MEM, 0x05 + 0x08 * (operation - IRREGULAR_BEGIN));
input_at (to == MEM, D32, destination, 0x1000);
}
static void build_special_1 (unsigned int operation) {
@ -181,6 +184,8 @@ static void build_jump_if (unsigned int operation, unsigned int size, unsigned i
input (far (location), 0x80 + operation - JUMP_IF_BEGIN);
input (near (location), 0x70 + operation - JUMP_IF_BEGIN);
input_at (1, D32, location, -(text_sector_size + 4));
}
static void build_move_if (unsigned int operation, unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {

1
source/eaxhla.l
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@ -205,7 +205,6 @@ popf { return ITPOPF; }
pushf { return ITPUSHF; }
retf { return ITRETF; }
retn { return ITRETN; }
sar { return ITSAR; }
sbb { return ITSBB; }
sub { return ITSUB; }
syscall { return ITSYSCALL; }

36
source/eaxhla.y
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@ -93,7 +93,7 @@
// Instructions
%token INOP
// #placeholder<instruction_token_list> BEGIN
%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSHF ITRETF ITRETN ITSAR ITSBB ITSUB ITSYSCALL ITXOR
%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSHF ITRETF ITRETN ITSBB ITSUB ITSYSCALL ITXOR
// #placeholder<instruction_token_list> END
// Instruction-likes
@ -484,16 +484,46 @@ instruction: INOP { append_instructions(NOP); }
| ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); }
| ITSBB register register { append_instructions( SBB, $2.size, REG, $2.number, REG, $3.number ); }
| ITAND register register { append_instructions( AND, $2.size, REG, $2.number, REG, $3.number ); }
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); }
| ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); }
| ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); }
| ITADD register immediate { append_instructions( ADD, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITOR register immediate { append_instructions( OR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITADC register immediate { append_instructions( ADC, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSBB register immediate { append_instructions( SBB, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSUB register immediate { append_instructions( SUB, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITXOR register immediate { append_instructions( XOR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITCMP register immediate { append_instructions( CMP, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITADD register memory { append_instructions( ADD, $2.size, REG, $2.number, MEM, $3 ); }
| ITOR register memory { append_instructions( OR, $2.size, REG, $2.number, MEM, $3 ); }
| ITADC register memory { append_instructions( ADC, $2.size, REG, $2.number, MEM, $3 ); }
| ITSBB register memory { append_instructions( SBB, $2.size, REG, $2.number, MEM, $3 ); }
| ITAND register memory { append_instructions( AND, $2.size, REG, $2.number, MEM, $3 ); }
| ITSUB register memory { append_instructions( SUB, $2.size, REG, $2.number, MEM, $3 ); }
| ITXOR register memory { append_instructions( XOR, $2.size, REG, $2.number, MEM, $3 ); }
| ITCMP register memory { append_instructions( CMP, $2.size, REG, $2.number, MEM, $3 ); }
| ITADD memory register { append_instructions( ADD, D32, MEM, $2, REG, $3.number ); }
| ITOR memory register { append_instructions( OR, D32, MEM, $2, REG, $3.number ); }
| ITADC memory register { append_instructions( ADC, D32, MEM, $2, REG, $3.number ); }
| ITSBB memory register { append_instructions( SBB, D32, MEM, $2, REG, $3.number ); }
| ITAND memory register { append_instructions( AND, D32, MEM, $2, REG, $3.number ); }
| ITSUB memory register { append_instructions( SUB, D32, MEM, $2, REG, $3.number ); }
| ITXOR memory register { append_instructions( XOR, D32, MEM, $2, REG, $3.number ); }
| ITCMP memory register { append_instructions( CMP, D32, MEM, $2, REG, $3.number ); }
| ITADD memory immediate { append_instructions( ADD, D32, MEM, $2, $3.type, $3.value ); }
| ITOR memory immediate { append_instructions( OR, D32, MEM, $2, $3.type, $3.value ); }
| ITADC memory immediate { append_instructions( ADC, D32, MEM, $2, $3.type, $3.value ); }
| ITSBB memory immediate { append_instructions( SBB, D32, MEM, $2, $3.type, $3.value ); }
| ITAND memory immediate { append_instructions( AND, D32, MEM, $2, $3.type, $3.value ); }
| ITSUB memory immediate { append_instructions( SUB, D32, MEM, $2, $3.type, $3.value ); }
| ITXOR memory immediate { append_instructions( XOR, D32, MEM, $2, $3.type, $3.value ); }
| ITCMP memory immediate { append_instructions( CMP, D32, MEM, $2, $3.type, $3.value ); }
| ITMOV register register { append_instructions( MOV, $2.size, REG, $2.number, REG, $3.number ); }
| ITMOV register immediate { append_instructions( MOV, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITMOV register memory { append_instructions( MOV, $2.size, REG, $2.number, MEM, $3 ); }
| ITMOV memory register { append_instructions( MOV, D32, MEM, $2, REG, $3.number ); }
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITMOV memory immediate { append_instructions( MOV, D32, MEM, $2, $3.type, $3.value ); }
// #placeholder<instruction_parser_rules> END
;

84
test/game_of_life.asm Normal file
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@ -0,0 +1,84 @@
format ELF64 executable 3
segment readable executable
entry main
char: nop
nop
mov eax, 1
nop
mov edi, 1
nop
mov edx, 1
nop
syscall
ret
main: nop
main_loop:
nop
mov dword[y], 0
begin_loop_y:
nop
cmp dword[y], 8
nop
je end_loop_y
nop
mov dword[x], 0
begin_loop_x:
nop
cmp dword[x], 8
nop
je end_loop_x
nop
mov esi, c
nop
call char
nop
inc dword[x]
nop
jmp begin_loop_x
end_loop_x:
nop
mov esi, c
nop
add esi, 2
nop
call char
nop
inc dword[y]
nop
jmp begin_loop_y
end_loop_y:
nop
mov esi, c
nop
add esi, 3
nop
call char
nop
inc esi
nop
call char
nop
inc esi
nop
call char
nop
jmp main_loop
nop
mov eax, 60
mov edi, 0
syscall
segment readable writable
y: dd 0
x: dd 0
p: dd 0
q: dd 0
f: db "..#.....#.#.......##............................................"
c: db ".#", 10, 27, "[H"
n: dd 0
b: db "..#.....#.#.......##............................................"

70
test/game_of_life.eax Normal file
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@ -0,0 +1,70 @@
fast procedure char
begin nop
nop mov eax 1 nop mov edi 1 nop mov edx 1 nop syscall
end procedure
unix program main
s8 <> f = "..#.....#.#.......##............................................"
s8 <> b = "..#.....#.#.......##............................................"
s8 <> c = ".#\n\e[H"
s32 y = 0
s32 x = 0
s32 p = 0
s32 q = 0
s32 n = 0
begin nop
main_loop:
nop mov [y] 0
begin_loop_y:
nop cmp [y] 8
nop je end_loop_y
nop mov [x] 0
begin_loop_x:
nop cmp [x] 8
nop je end_loop_x
nop mov esi c
nop fastcall char
nop inc [x]
nop jmp begin_loop_x
end_loop_x:
nop mov esi c
nop add esi 2
nop fastcall char
nop inc [y]
nop jmp begin_loop_y
end_loop_y:
nop mov esi c
nop add esi 3
nop fastcall char
nop inc esi
nop fastcall char
nop inc esi
nop fastcall char
nop jmp main_loop
nop exit 0
end program
/*
x,y,p,q,f[12][24],b[12][24],n;
main(){
f[0][1]=f[1][2]=f[2][0]=f[2][1]=f[2][2]=1;
l:
for(y=0;y<12;++y){
for(x=0;x<24;++x){
n=0;
for(q=-1;q<2;++q)
for(p=-1;p<2;++p)
if(p!=0||q!=0)
if(f[((y+q)%12+12)%12][((x+p)%24+24)%24])
n+=1;
b[y][x]=f[y][x]?(n==2||n==3):n==3;
printf("%c",".#"[f[y][x]]);
}
printf("\012");
}
printf("\033[H");
memcpy(f,b,1152);
usleep(100000);
goto l;
}
*/

34
tool/generators/instructions.tcl
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@ -60,16 +60,46 @@ set instructions {
{adc register register}
{sbb register register}
{and register register}
{and register immediate}
{sub register register}
{xor register register}
{cmp register register}
{add register immediate}
{or register immediate}
{adc register immediate}
{sbb register immediate}
{and register immediate}
{sub register immediate}
{xor register immediate}
{cmp register immediate}
{add register memory}
{or register memory}
{adc register memory}
{sbb register memory}
{and register memory}
{sub register memory}
{xor register memory}
{cmp register memory}
{add memory register}
{or memory register}
{adc memory register}
{sbb memory register}
{and memory register}
{sub memory register}
{xor memory register}
{cmp memory register}
{add memory immediate}
{or memory immediate}
{adc memory immediate}
{sbb memory immediate}
{and memory immediate}
{sub memory immediate}
{xor memory immediate}
{cmp memory immediate}
{mov register register}
{mov register immediate}
{mov register memory}
{mov memory register}
{sar register immediate}
{mov memory immediate}
}
proc malformed_instruction {i} {