a bunch of stuff
This commit is contained in:
anon
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549937a53a
commit
c17348f18d
@ -10,6 +10,8 @@ endif
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"runtime! syntax/c.vim
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"unlet b:current_syntax
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syn iskeyword @,48-57,_
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syn region eaxSingleLineComment start=+//+ end=+\n+
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syn region eaxSingleLineComment2 start=+#+ end=+\n+
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syn region eaxMultiLineComment start=+\/\*+ end=+\*\/+
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@ -18,7 +20,11 @@ syn keyword eaxKeyword program machine procedure begin until repeat break if the
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syn keyword eaxType u8 u16 u32 u64 s8 s16 s32 s64
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syn keyword eaxInstruction inc xor mov
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syn keyword eaxInstructionLike fastcall exit
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syn keyword eaxRegister rax rbx rcx rdx rbp rsp rip rdi r7 r8 r9 r10 r11 r12 r13 r14 r15
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syn keyword eaxRegister
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\ rax rcx rdx rbx rsp rbp rsi rdi rg8 rg9 rg10 rg11 rg12 rg13 rg14 rg15
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\ eax ecx edx ebx esp ebp esi edi rg8d rg9d rg10d rg11d rg12d rg13d rg14d rg15d
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\ ax cx dx bx sp bp si di r8w r9w r10w r11w r12w r13w r14w r15w
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\ al cl dl bl spl bpl sil dil r8b r9b r10b r11b r12b r13b r14b r15b
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syn match eaxInt "\-\?\d\+"
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syn match eaxHex "0x[0-9a-fA-F]\+"
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syn match eaxBin "0b\[01\]\+"
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@ -128,8 +128,8 @@ void _append_instructions(const unsigned argc, ...) {
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void append_exit(int code) {
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if (system_type == UNIX) {
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append_instructions(MOV, D32, REG, R0, IMM, 60,
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MOV, D32, REG, R7, IMM, code,
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append_instructions(MOV, D32, REG, GR0, IMM, 60,
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MOV, D32, REG, GR7, IMM, code,
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SYSCALL
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);
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}
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@ -17,31 +17,34 @@
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#include "assembler.h"
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#include "compile.h"
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int has_encountered_error = 0;
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int is_program_found = 0;
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char * yyfilename = "";
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static symbol_t * undeclared_symbol;
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/* Used for naming variables constructed from literals
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*/
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size_t anon_variable_counter = 0;
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static size_t anon_variable_counter = 0;
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/* Used to check whether all labels without
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* previous declarations (forward jumps)
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* have been declared later in code
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*/
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size_t unresolved_label_counter = 0;
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static size_t unresolved_label_counter = 0;
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static unsigned symbol_id = 1;
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tommy_hashtable symbol_table;
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int has_encountered_error = 0;
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int is_program_found = 0;
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char * scope = NULL;
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static char * scope = NULL;
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void empty_out_scope(void) {
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free(scope);
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scope = NULL;
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}
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char * yyfilename = "";
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int eaxhla_init(void) {
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undeclared_symbol = (symbol_t *)calloc(sizeof(symbol_t), 1);
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tommy_hashtable_init(&symbol_table, 256);
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return 0;
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}
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@ -74,6 +77,7 @@ void free_symbol(void * data) {
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int eaxhla_deinit(void) {
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empty_out_scope();
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free(undeclared_symbol);
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tommy_hashtable_foreach(&symbol_table, free_symbol);
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tommy_hashtable_done(&symbol_table);
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@ -207,8 +211,8 @@ void add_program(const char * const name) {
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static
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void _add_variable(unsigned type, const char * const name, size_t size, void * value) {
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char * full_name = make_scoped_name(scope, name);
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if (get_variable(full_name)) {
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issue_error("symbol '%s' redeclared as new variable", full_name);
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if (get_symbol(name)) {
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issue_error("symbol '%s' redeclared as new variable", name);
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return;
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}
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@ -384,8 +388,12 @@ symbol_t * get_variable(const char * const name) {
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if (r
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&& r->symbol_type != VARIABLE_SYMBOL) {
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issue_error("the symbol '%s' is not a variable", name);
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r = NULL;
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}
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if (!r) {
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r = undeclared_symbol;
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}
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free(varname);
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return r;
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}
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@ -33,8 +33,10 @@ typedef struct {
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} symbol_t;
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/* private:
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symbol_t * new_symbol(const char * const name);
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void free_symbol(void * name);
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*/
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extern tommy_hashtable symbol_table;
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@ -6,6 +6,8 @@
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sds string_literal_buffer;
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long char_literal_buffer = 0;
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#define YY_USER_INIT \
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string_literal_buffer = sdsnew("");
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%}
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@ -18,7 +20,7 @@ hex [0123456789abcdef]
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uhex [0123456789ABCDEF]
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%x IN_COMMENT IN_MULTILINE_COMMENT
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%x IN_STRING
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%x IN_CHAR IN_STRING
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%x IN_END IN_UNKNOWN_END
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%x IN_ARTIMETRIC_BLOCK
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@ -48,11 +50,7 @@ end { BEGIN IN_END; }
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fast { return FAST; }
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unix { return UNIX; }
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/* #placeholder<register_scanner_instructions> END
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*/
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in { return TIN; }
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\= { return '='; }
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s8 { return S8; }
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s16 { return S16; }
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@ -63,6 +61,7 @@ u16 { return U16; }
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u32 { return U32; }
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u64 { return U64; }
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\' { BEGIN IN_CHAR; }
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\" { BEGIN IN_STRING; }
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\!\= { return ITNEQ; }
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@ -71,7 +70,7 @@ u64 { return U64; }
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(\/\/)|\# { BEGIN IN_COMMENT; }
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\/\* { BEGIN IN_MULTILINE_COMMENT; }
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\[|\]|\{|\}|\+|\-|\*|\/|\%|\^|\:|\<|\> {
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\[|\]|\{|\}|\+|\-|\*|\/|\%|\^|\:|\<|\>|\= {
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return yytext[0];
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}
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@ -88,14 +87,14 @@ rsp { return RSP; }
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rbp { return RBP; }
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rsi { return RSI; }
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rdi { return RDI; }
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rg8 { return RG8; }
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rg9 { return RG9; }
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rg10 { return RG10; }
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rg11 { return RG11; }
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rg12 { return RG12; }
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rg13 { return RG13; }
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rg14 { return RG14; }
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rg15 { return RG15; }
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r8 { return R8; }
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r9 { return R9; }
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r10 { return R10; }
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r11 { return R11; }
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r12 { return R12; }
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r13 { return R13; }
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r14 { return R14; }
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r15 { return R15; }
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eax { return EAX; }
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ecx { return ECX; }
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edx { return EDX; }
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@ -104,14 +103,14 @@ esp { return ESP; }
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ebp { return EBP; }
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esi { return ESI; }
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edi { return EDI; }
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rg8d { return RG8D; }
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rg9d { return RG9D; }
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rg10d { return RG10D; }
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rg11d { return RG11D; }
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rg12d { return RG12D; }
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rg13d { return RG13D; }
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rg14d { return RG14D; }
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rg15d { return RG15D; }
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r8d { return R8D; }
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r9d { return R9D; }
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r10d { return R10D; }
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r11d { return R11D; }
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r12d { return R12D; }
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r13d { return R13D; }
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r14d { return R14D; }
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r15d { return R15D; }
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ax { return AX; }
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cx { return CX; }
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dx { return DX; }
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@ -163,7 +162,9 @@ hlt { return ITHLT; }
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idiv { return ITIDIV; }
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imul { return ITIMUL; }
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inc { return ITINC; }
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je { return ITJE; }
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jmp { return ITJMP; }
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jne { return ITJNE; }
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leave { return ITLEAVE; }
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lock { return ITLOCK; }
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mov { return ITMOV; }
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@ -172,6 +173,7 @@ neg { return ITNEG; }
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not { return ITNOT; }
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or { return ITOR; }
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pause { return ITPAUSE; }
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pop { return ITPOP; }
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retf { return ITRETF; }
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retn { return ITRETN; }
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sar { return ITSAR; }
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@ -202,12 +204,25 @@ library { BEGIN INITIAL; return END_LIBRARY; }
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.* { issue_error("unknown end-sequence \033[1m'%s'\033[0m", yytext); BEGIN INITIAL; return 0; }
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}
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<IN_STRING>{
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/* XXX: the first WORD_SIZE_IN_BYTES bytes should be 0'd */
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<IN_CHAR>{
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/* XXX: i wanted short strings to be literals;
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this however clashes with with the sanity of machine blocks;
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those should be moved to '' (exactly like in Holy C)
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*/
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/* XXX: THIS CODE IS TOTAL DEATH
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*/
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. { char_literal_buffer = yytext[0]; }
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\n { char_literal_buffer = '\n'; }
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\' {
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yylval.intval = char_literal_buffer;
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char_literal_buffer = 0;
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return LITERAL;
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}
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\n { issue_error("unterminated character literal sequence"); yyterminate(); }
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}
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<IN_STRING>{
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/* XXX: the first WORD_SIZE_IN_BYTES bytes should be 0'd */
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\" {
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BEGIN INITIAL;
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yylval.blobval.data = malloc(sdslen(string_literal_buffer));
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163
source/eaxhla.y
163
source/eaxhla.y
@ -83,8 +83,8 @@
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%type<regval> register register64s register32s register16s register8s
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// #placeholder<register_token_list> BEGIN
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%token RAX RCX RDX RBX RSP RBP RSI RDI RG8 RG9 RG10 RG11 RG12 RG13 RG14 RG15
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%token EAX ECX EDX EBX ESP EBP ESI EDI RG8D RG9D RG10D RG11D RG12D RG13D RG14D RG15D
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%token RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15
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%token EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D
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%token AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W
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%token AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B
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@ -93,7 +93,7 @@
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// Instructions
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%token INOP
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// #placeholder<instruction_token_list> BEGIN
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%token ITADC ITADD ITAND ITCMP ITDEC ITDIV ITHLT ITIDIV ITIMUL ITINC ITJMP ITLEAVE ITLOCK ITMOV ITMUL ITNEG ITNOT ITOR ITPAUSE ITRETF ITRETN ITSAR ITSBB ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITXOR
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%token ITADC ITADD ITAND ITCMP ITDEC ITDIV ITHLT ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITLOCK ITMOV ITMUL ITNEG ITNOT ITOR ITPAUSE ITPOP ITRETF ITRETN ITSAR ITSBB ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITXOR
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// #placeholder<instruction_token_list> END
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// Instruction-likes
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@ -204,7 +204,10 @@ memory: artimetric_block
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| dereference
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;
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dereference: '[' IDENTIFIER ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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dereference: '[' IDENTIFIER ']' {
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$$ = get_variable($2)->_id;
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free($2);
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}
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| '[' IDENTIFIER '+' value ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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| '[' IDENTIFIER '-' value ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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;
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@ -312,76 +315,76 @@ register: register64s { $$ = $1; $$.size = D64; }
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;
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// #placeholder<register_parser_rules> BEGIN
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register64s: RAX { $$.number = R0; }
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| RCX { $$.number = R1; }
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| RDX { $$.number = R2; }
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| RBX { $$.number = R3; }
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| RSP { $$.number = R4; }
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| RBP { $$.number = R5; }
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| RSI { $$.number = R6; }
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| RDI { $$.number = R7; }
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| RG8 { $$.number = R8; }
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| RG9 { $$.number = R9; }
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| RG10 { $$.number = R10; }
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| RG11 { $$.number = R11; }
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| RG12 { $$.number = R12; }
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| RG13 { $$.number = R13; }
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| RG14 { $$.number = R14; }
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| RG15 { $$.number = R15; }
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register64s: RAX { $$.number = GR0; }
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| RCX { $$.number = GR1; }
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| RDX { $$.number = GR2; }
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| RBX { $$.number = GR3; }
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| RSP { $$.number = GR4; }
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| RBP { $$.number = GR5; }
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| RSI { $$.number = GR6; }
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| RDI { $$.number = GR7; }
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| R8 { $$.number = GR8; }
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| R9 { $$.number = GR9; }
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| R10 { $$.number = GR10; }
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| R11 { $$.number = GR11; }
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| R12 { $$.number = GR12; }
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| R13 { $$.number = GR13; }
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| R14 { $$.number = GR14; }
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| R15 { $$.number = GR15; }
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;
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register32s: EAX { $$.number = R0; }
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| ECX { $$.number = R1; }
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| EDX { $$.number = R2; }
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| EBX { $$.number = R3; }
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| ESP { $$.number = R4; }
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| EBP { $$.number = R5; }
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| ESI { $$.number = R6; }
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| EDI { $$.number = R7; }
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| RG8D { $$.number = R8; }
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| RG9D { $$.number = R9; }
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| RG10D { $$.number = R10; }
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| RG11D { $$.number = R11; }
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| RG12D { $$.number = R12; }
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| RG13D { $$.number = R13; }
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| RG14D { $$.number = R14; }
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| RG15D { $$.number = R15; }
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register32s: EAX { $$.number = GR0; }
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| ECX { $$.number = GR1; }
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| EDX { $$.number = GR2; }
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| EBX { $$.number = GR3; }
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| ESP { $$.number = GR4; }
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| EBP { $$.number = GR5; }
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| ESI { $$.number = GR6; }
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| EDI { $$.number = GR7; }
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| R8D { $$.number = GR8; }
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| R9D { $$.number = GR9; }
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| R10D { $$.number = GR10; }
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| R11D { $$.number = GR11; }
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| R12D { $$.number = GR12; }
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| R13D { $$.number = GR13; }
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| R14D { $$.number = GR14; }
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| R15D { $$.number = GR15; }
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;
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register16s: AX { $$.number = R0; }
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| CX { $$.number = R1; }
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| DX { $$.number = R2; }
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| BX { $$.number = R3; }
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| SP { $$.number = R4; }
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| BP { $$.number = R5; }
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| SI { $$.number = R6; }
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| DI { $$.number = R7; }
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| R8W { $$.number = R8; }
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| R9W { $$.number = R9; }
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| R10W { $$.number = R10; }
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| R11W { $$.number = R11; }
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| R12W { $$.number = R12; }
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| R13W { $$.number = R13; }
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| R14W { $$.number = R14; }
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| R15W { $$.number = R15; }
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register16s: AX { $$.number = GR0; }
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| CX { $$.number = GR1; }
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| DX { $$.number = GR2; }
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| BX { $$.number = GR3; }
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| SP { $$.number = GR4; }
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| BP { $$.number = GR5; }
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| SI { $$.number = GR6; }
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| DI { $$.number = GR7; }
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| R8W { $$.number = GR8; }
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| R9W { $$.number = GR9; }
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| R10W { $$.number = GR10; }
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| R11W { $$.number = GR11; }
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| R12W { $$.number = GR12; }
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| R13W { $$.number = GR13; }
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| R14W { $$.number = GR14; }
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| R15W { $$.number = GR15; }
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;
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register8s: AL { $$.number = R0; }
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| CL { $$.number = R1; }
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| DL { $$.number = R2; }
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| BL { $$.number = R3; }
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| SPL { $$.number = R4; }
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| BPL { $$.number = R5; }
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| SIL { $$.number = R6; }
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| DIL { $$.number = R7; }
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| R8B { $$.number = R8; }
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| R9B { $$.number = R9; }
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| R10B { $$.number = R10; }
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| R11B { $$.number = R11; }
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| R12B { $$.number = R12; }
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| R13B { $$.number = R13; }
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| R14B { $$.number = R14; }
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| R15B { $$.number = R15; }
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register8s: AL { $$.number = GR0; }
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| CL { $$.number = GR1; }
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| DL { $$.number = GR2; }
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| BL { $$.number = GR3; }
|
||||
| SPL { $$.number = GR4; }
|
||||
| BPL { $$.number = GR5; }
|
||||
| SIL { $$.number = GR6; }
|
||||
| DIL { $$.number = GR7; }
|
||||
| R8B { $$.number = GR8; }
|
||||
| R9B { $$.number = GR9; }
|
||||
| R10B { $$.number = GR10; }
|
||||
| R11B { $$.number = GR11; }
|
||||
| R12B { $$.number = GR12; }
|
||||
| R13B { $$.number = GR13; }
|
||||
| R14B { $$.number = GR14; }
|
||||
| R15B { $$.number = GR15; }
|
||||
;
|
||||
|
||||
|
||||
@ -431,6 +434,8 @@ instruction: INOP { append_instructions(NOP); }
|
||||
| ITHLT { append_instructions(HLT); }
|
||||
| ITLOCK { append_instructions(LOCK); }
|
||||
| ITJMP relative { append_instructions( JMP, D32, REL, $2 ); }
|
||||
| ITJE relative { append_instructions( JE, D32, REL, $2 ); }
|
||||
| ITJNE relative { append_instructions( JNE, D32, REL, $2 ); }
|
||||
| ITINC register { append_instructions( INC, $2.size, REG, $2.number ); }
|
||||
| ITDEC register { append_instructions( DEC, $2.size, REG, $2.number ); }
|
||||
| ITNOT register { append_instructions( NOT, $2.size, REG, $2.number ); }
|
||||
@ -439,14 +444,15 @@ instruction: INOP { append_instructions(NOP); }
|
||||
| ITIMUL register { append_instructions( IMUL, $2.size, REG, $2.number ); }
|
||||
| ITDIV register { append_instructions( DIV, $2.size, REG, $2.number ); }
|
||||
| ITIDIV register { append_instructions( IDIV, $2.size, REG, $2.number ); }
|
||||
| ITINC memory { append_instructions( INC, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITDEC memory { append_instructions( DEC, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITNOT memory { append_instructions( NOT, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITNEG memory { append_instructions( NEG, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITMUL memory { append_instructions( MUL, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITIMUL memory { append_instructions( IMUL, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITDIV memory { append_instructions( DIV, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITIDIV memory { append_instructions( IDIV, 0 /* ??? */, MEM, 0 /* ??? */ ); }
|
||||
| ITPOP register { append_instructions( POP, $2.size, REG, $2.number ); }
|
||||
| ITINC memory { append_instructions( INC, D32, MEM, $2 ); }
|
||||
| ITDEC memory { append_instructions( DEC, D32, MEM, $2 ); }
|
||||
| ITNOT memory { append_instructions( NOT, D32, MEM, $2 ); }
|
||||
| ITNEG memory { append_instructions( NEG, D32, MEM, $2 ); }
|
||||
| ITMUL memory { append_instructions( MUL, D32, MEM, $2 ); }
|
||||
| ITIMUL memory { append_instructions( IMUL, D32, MEM, $2 ); }
|
||||
| ITDIV memory { append_instructions( DIV, D32, MEM, $2 ); }
|
||||
| ITIDIV memory { append_instructions( IDIV, D32, MEM, $2 ); }
|
||||
| ITADD register register { append_instructions( ADD, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITOR register register { append_instructions( OR, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
@ -455,9 +461,12 @@ instruction: INOP { append_instructions(NOP); }
|
||||
| ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITCMP register immediate { append_instructions( CMP, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITMOV register register { append_instructions( MOV, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITMOV register immediate { append_instructions( MOV, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITMOV register memory { append_instructions( MOV, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITMOV memory register { append_instructions( MOV, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
|
||||
// #placeholder<instruction_parser_rules> END
|
||||
;
|
||||
|
||||
18
test/if.eax
Normal file
18
test/if.eax
Normal file
@ -0,0 +1,18 @@
|
||||
program basic_conditional
|
||||
begin
|
||||
if 0 then
|
||||
mov eax 1
|
||||
mov edi 1
|
||||
mov esi "nope\n"
|
||||
mov edx 5
|
||||
syscall
|
||||
end if
|
||||
|
||||
if 1 then
|
||||
mov eax 1
|
||||
mov edi 1
|
||||
mov esi "yup\n"
|
||||
mov edx 4
|
||||
syscall
|
||||
end if
|
||||
end program
|
||||
@ -26,7 +26,7 @@ begin
|
||||
end procedure
|
||||
|
||||
fast procedure write_space
|
||||
s8 space = " "
|
||||
s8 space = ' '
|
||||
begin
|
||||
mov eax 1
|
||||
mov edi 1
|
||||
@ -36,7 +36,7 @@ begin
|
||||
end procedure
|
||||
|
||||
fast procedure write_line_feed
|
||||
s8 line_feed = "\n"
|
||||
s8 line_feed = '\n'
|
||||
begin
|
||||
mov eax 1
|
||||
mov edi 1
|
||||
@ -74,7 +74,7 @@ begin
|
||||
main_loop:
|
||||
mov r12d [file]
|
||||
mov r13d byte
|
||||
call read_character
|
||||
fastcall read_character
|
||||
|
||||
mov r10d eax
|
||||
mov r15b [byte]
|
||||
|
||||
@ -10,20 +10,20 @@ proc make_parser_rules {is} {
|
||||
dict set r size "\$$n.size"
|
||||
}
|
||||
"immediate" {
|
||||
dict set r enum "$$n.type"
|
||||
dict set r value "$$n.value"
|
||||
dict set r enum "\$$n.type"
|
||||
dict set r value "\$$n.value"
|
||||
# XXX
|
||||
dict set r size "D32"
|
||||
}
|
||||
"relative" {
|
||||
dict set r enum "REL"
|
||||
dict set r value "$$n"
|
||||
dict set r value "\$$n"
|
||||
dict set r size "D32"
|
||||
}
|
||||
"memory" {
|
||||
dict set r enum "MEM"
|
||||
dict set r value "0 /* ??? */"
|
||||
dict set r size "0 /* ??? */"
|
||||
dict set r value "\$$n"
|
||||
dict set r size "D32"
|
||||
}
|
||||
default { malformed_instruction $n }
|
||||
}
|
||||
|
||||
@ -10,6 +10,8 @@ set instructions {
|
||||
{hlt}
|
||||
{lock}
|
||||
{jmp relative}
|
||||
{je relative}
|
||||
{jne relative}
|
||||
{inc register}
|
||||
{dec register}
|
||||
{not register}
|
||||
@ -18,6 +20,7 @@ set instructions {
|
||||
{imul register}
|
||||
{div register}
|
||||
{idiv register}
|
||||
{pop register}
|
||||
{inc memory}
|
||||
{dec memory}
|
||||
{not memory}
|
||||
@ -34,9 +37,12 @@ set instructions {
|
||||
{sub register register}
|
||||
{xor register register}
|
||||
{cmp register register}
|
||||
{sar register immediate}
|
||||
{cmp register immediate}
|
||||
{mov register register}
|
||||
{mov register immediate}
|
||||
{mov register memory}
|
||||
{mov memory register}
|
||||
{sar register immediate}
|
||||
}
|
||||
|
||||
proc malformed_instruction {i} {
|
||||
|
||||
@ -2,13 +2,13 @@ source tool/generators/registers.tcl
|
||||
|
||||
proc register_parsing {registers} {
|
||||
proc register_parser_rule {size batch} {
|
||||
puts [format "register%ss: %s \{ \$\$.number = R0; \}"\
|
||||
puts [format "register%ss: %s \{ \$\$.number = GR0; \}"\
|
||||
$size\
|
||||
[string toupper [lindex $batch 0]]\
|
||||
]
|
||||
set accumulator 1
|
||||
foreach register [lrange $batch 1 end] {
|
||||
puts [format " | %-5s \{ \$\$.number = R%s; \}"\
|
||||
puts [format " | %-5s \{ \$\$.number = GR%s; \}"\
|
||||
[string toupper $register]\
|
||||
$accumulator\
|
||||
]
|
||||
|
||||
@ -3,7 +3,10 @@ source tool/generators/registers.tcl
|
||||
proc scan_registers {registers} {
|
||||
foreach {key value} $registers {
|
||||
foreach {register} $value {
|
||||
puts [format "%-6s \{ return %s; \}" $register [string toupper $register]]
|
||||
puts [format "%-6s \{ return %s; \}"\
|
||||
$register\
|
||||
[string toupper $register]\
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,14 +1,3 @@
|
||||
# XXX
|
||||
#
|
||||
# | RGXMM0 { $$.number = 0; } /* XXX */
|
||||
# | RGXMM1 { $$.number = 0; }
|
||||
# | RGXMM2 { $$.number = 0; }
|
||||
# | RGXMM3 { $$.number = 0; }
|
||||
# | RGXMM4 { $$.number = 0; }
|
||||
# | RGXMM5 { $$.number = 0; }
|
||||
# | RGXMM6 { $$.number = 0; }
|
||||
# | RGXMM7 { $$.number = 0; }
|
||||
|
||||
set register64s {
|
||||
rax
|
||||
rcx
|
||||
@ -18,14 +7,14 @@ set register64s {
|
||||
rbp
|
||||
rsi
|
||||
rdi
|
||||
rg8
|
||||
rg9
|
||||
rg10
|
||||
rg11
|
||||
rg12
|
||||
rg13
|
||||
rg14
|
||||
rg15
|
||||
r8
|
||||
r9
|
||||
r10
|
||||
r11
|
||||
r12
|
||||
r13
|
||||
r14
|
||||
r15
|
||||
}
|
||||
|
||||
set register32s {
|
||||
@ -37,14 +26,14 @@ set register32s {
|
||||
ebp
|
||||
esi
|
||||
edi
|
||||
rg8d
|
||||
rg9d
|
||||
rg10d
|
||||
rg11d
|
||||
rg12d
|
||||
rg13d
|
||||
rg14d
|
||||
rg15d
|
||||
r8d
|
||||
r9d
|
||||
r10d
|
||||
r11d
|
||||
r12d
|
||||
r13d
|
||||
r14d
|
||||
r15d
|
||||
}
|
||||
|
||||
set register16s {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user