Merge branch 'master' of https://codeberg.org/eaxcc/eaxcc
This commit is contained in:
anon
commit
e171fddcae
@ -7,9 +7,9 @@
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#define IRREGULAR_BEGIN (INC)
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#define IRREGULAR_END (IDIV)
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#define SPECIAL_1_BEGIN (NOP)
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#define SPECIAL_1_END (STOSD)
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#define SPECIAL_2_BEGIN (SYSENTER)
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#define SPECIAL_2_END (XLATB)
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#define SPECIAL_1_END (PUSHF)
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#define SPECIAL_2_BEGIN (SYSCALL)
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#define SPECIAL_2_END (FCOS)
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#define JUMP_IF_BEGIN (JO)
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#define JUMP_IF_END (JG)
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#define MOVE_IF_BEGIN (CMOVO)
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@ -87,30 +87,29 @@ static int near (unsigned int label) {
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return (label && 0);
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}
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static void build_short_prefix (int when) {
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input (when, 0x66);
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static void short_prefix (unsigned int size) {
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input (size == D16, 0x66);
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}
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static void build_long_prefix (unsigned int registers, unsigned int to, unsigned int from) {
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input (registers || to || from, 0x40 + 0x01 * to + 0x04 * from + 0x08 * registers);
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static void long_prefix (unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
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int to_upper = (to == REG) && (upper (destination));
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int from_upper = (from == REG) && (upper (source));
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input ((size == D64) || (to_upper) || (from_upper), 0x40 + 0x01 * to_upper + 0x04 * from_upper + 0x08 * (size == D64));
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}
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static void build_co (int when, unsigned int destination, unsigned int source) {
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input (when, 0xc0 + 0x01 * (destination & 0x07) + 0x08 * (source & 0x07));
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static void modify_registers (unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
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input ((to == REG) && (from == REG), 0xc0 + 0x01 * (destination & 0x07) + 0x08 * (source & 0x07));
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}
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static void build_at (int when, unsigned int direction) {
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input (when, 0x05 + 0x08 * (direction & 0x07));
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}
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static void build_constant (int when, unsigned int size) {
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input (when, 0x80 + 0x01 * (size != D8));
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static void modify_memory (unsigned int operation, unsigned int to, unsigned int from) {
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input (((to == MEM) && (from == REG)) || ((to == REG) && (from == MEM)), 0x05 + 0x08 * operation * ((to == MEM) && (from == IMM)));
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}
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static void build_regular (unsigned int operation, unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
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build_short_prefix (size == D16);
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short_prefix (size);
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build_long_prefix (size == D64, (to == REG) && (upper (destination)), (from == REG) && (upper (source)));
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long_prefix (size, to, destination, from, source);
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input ((size == D8) && (to == REG)
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&& ((from == REG) || (from == IMM))
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@ -119,9 +118,9 @@ static void build_regular (unsigned int operation, unsigned int size, unsigned i
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|| ((to == REG) && (from == IMM) && front (destination))),
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0x40);
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input ((from == IMM) && (to == REG) && (destination == 0), 0x05 + 0x08 * (operation & 0x07) - 0x01 * (size == D8));
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input ((from == IMM) && (to == REG), 0x81 - 0x01 * (size == D8));
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build_constant ((from == IMM) && ! ((to == REG) && (destination == 0)), size);
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input ((from == IMM) && (to == REG) && (destination == 0), 0x05 + 0x08 * (operation & 0x07) - 0x01 * (size == D8));
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input (! ((from == IMM) && (to == REG) && (destination == 0)),
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(destination & 0x07) * ((to == REG) && (from == IMM))
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@ -133,22 +132,23 @@ static void build_regular (unsigned int operation, unsigned int size, unsigned i
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+ 0x04 * ((to == MEM) && (from == IMM))
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+ 0xc0 * ((to == REG) && (from == IMM)));
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build_co ((to == REG) && (from == REG), destination, source);
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modify_registers (to, destination, from, source);
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build_at ((to == REG) && (from == MEM), destination);
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build_at ((to == MEM) && (from == REG), source);
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modify_memory (destination, to, from);
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modify_memory (source, to, from);
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input_by ((to == REG) && (from == MEM), D32, ~0x0u);
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input_at ((to == REG) && (from == MEM), D32, source, 0x1000 - (text_sector_size + 4));
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input_by ((to == REG) && (from == IMM), size, source);
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input_by ((to == MEM) && (from == REG), D32, ~0x0u);
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input_by ((to == MEM) && (from == IMM), D32, ~0x0u);
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input_at ((to == MEM) && (from == REG), D32, destination, 0x1000 - (text_sector_size + 4));
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input_at ((to == MEM) && (from == IMM), D32, destination, 0x1000 - (text_sector_size + 4));
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input_by ((to == MEM) && (from == IMM), size, source);
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input_at ((to == REG) && (from == REL), D32, source, 0x4010b0 - (text_sector_size + 4));
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}
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static void build_irregular (unsigned int operation, unsigned int size, unsigned int to, unsigned int destination) {
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build_short_prefix (size == D16);
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short_prefix (size);
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build_long_prefix (size == D64, (to == REG) && (upper (destination)), 0);
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long_prefix (size, to, destination, 0, 0);
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input ((size == D8) && (to == REG) && front (destination), 0x40);
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@ -156,12 +156,13 @@ static void build_irregular (unsigned int operation, unsigned int size, unsigned
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input (to == REG, 0xc0 + 0x08 * (operation - IRREGULAR_BEGIN) + 0x01 * (destination & 0x07));
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input (to == MEM, 0x05 + 0x08 * (operation - IRREGULAR_BEGIN));
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input_at (to == MEM, D32, destination, 0x1000 - (text_sector_size + 4));
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}
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static void build_special_1 (unsigned int operation) {
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const unsigned char data [] = {
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0x90, 0xc3, 0xcb, 0xc9, 0xf0, 0xf4, 0x9d, 0x9c, 0x9b, 0xf8, 0xfc, 0xfa, 0xf9, 0xfd, 0xfb, 0xf5, 0x6c, 0x6d, 0x6e, 0x6f, 0x99, 0x98, 0xec, 0xed, 0xcc, 0xcf, 0xac,
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0xad, 0xee, 0xef, 0xae, 0xaf, 0xaa, 0xab
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0x90, 0xc3, 0xcb, 0xc9, 0x9d, 0x9c
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};
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input (1, data [operation - SPECIAL_1_BEGIN]);
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@ -169,9 +170,10 @@ static void build_special_1 (unsigned int operation) {
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static void build_special_2 (unsigned int operation) {
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const unsigned short data [] = {
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0x340f, 0x350f, 0x050f, 0x070f, 0x90f3, 0xa20f, 0x770f, 0xaa0f, 0xd0d9, 0xe0d9, 0xe1d9, 0xe4d9, 0xe5d9, 0xe8d9, 0xe9d9, 0xead9, 0xebd9, 0xecd9, 0xedd9, 0xeed9,
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0xf0d9, 0xf1d9, 0xf2d9, 0xf3d9, 0xf4d9, 0xf5d9, 0xf6d9, 0xf7d9, 0xf8d9, 0xf9d9, 0xfad9, 0xfbd9, 0xfcd9, 0xfdd9, 0xfed9, 0xffd9, 0x6d66, 0x6f66, 0x9966, 0x9948,
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0x9866, 0x9848, 0x080f, 0x090f, 0x0b0f, 0x060f, 0xed66, 0xcf48, 0xad66, 0xad48, 0xef66, 0x330f, 0x320f, 0x310f, 0xaf66, 0xaf48, 0xab66, 0xab48, 0x300f, 0xd748
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0x050f, 0xa20f, 0xd0d9, 0xe0d9, 0xe1d9, 0xe4d9, 0xe5d9, 0xe8d9,
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0xe9d9, 0xead9, 0xebd9, 0xecd9, 0xedd9, 0xeed9, 0xf0d9, 0xf1d9,
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0xf2d9, 0xf3d9, 0xf4d9, 0xf5d9, 0xf6d9, 0xf7d9, 0xf8d9, 0xf9d9,
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0xfad9, 0xfbd9, 0xfcd9, 0xfdd9, 0xfed9, 0xffd9
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};
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input_by (1, D16, data [operation - SPECIAL_2_BEGIN]);
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@ -184,18 +186,20 @@ static void build_jump_if (unsigned int operation, unsigned int size, unsigned i
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input (far (location), 0x80 + operation - JUMP_IF_BEGIN);
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input (near (location), 0x70 + operation - JUMP_IF_BEGIN);
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input_at (1, D32, location, -(text_sector_size + 4));
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}
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static void build_move_if (unsigned int operation, unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
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build_short_prefix (size == D16);
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short_prefix (size);
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build_long_prefix (size == D64, (to == REG) && (upper (destination)), (from == REG) && (upper (source)));
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long_prefix (size, to, destination, from, source);
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input (1, 0x0f);
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input (1, 0x40 + operation - MOVE_IF_BEGIN);
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build_co ((to == REG) && (from == REG), destination, source);
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build_at ((to == REG) && (from == MEM), destination);
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modify_registers (to, destination, from, source);
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modify_memory (destination, to, from);
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}
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static void build_jump (unsigned int size, unsigned int to, unsigned int destination) {
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@ -212,28 +216,28 @@ static void build_jump (unsigned int size, unsigned int to, unsigned int destina
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}
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static void build_move (unsigned int size, unsigned int to, unsigned int destination, unsigned int from, unsigned int source) {
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build_short_prefix (size == D16);
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short_prefix (size);
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build_long_prefix (size == D64, (to == REG) && (upper (destination)), (from == REG) && (upper (source)));
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long_prefix (size, to, destination, from, source);
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input ((to == REG) && (from == REG), 0x88 + 0x01 * (size != D8));
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input ((to == REG) && (from == MEM), 0x8a + 0x01 * (size != D8));
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input ((to == MEM) && (from == REG), 0x88 + 0x01 * (size != D8));
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build_at ((to == REG) && (from == MEM), destination);
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build_at ((to == MEM) && (from == REG), source);
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modify_memory (destination, to, from);
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modify_memory (source, to, from);
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build_co ((to == REG) && (from == REG), destination, source);
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modify_registers (to, destination, from, source);
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input ((to == REG) && ((from == IMM) || (from == REL)), 0xb8 + 0x01 * (destination & 0x07));
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input ((to == MEM) && (from == IMM), 0xc6 + 0x01 * (size != D8));
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input ((to == MEM) && (from == IMM), 0x05);
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input_at ((to == REG) && (from == MEM), D32, source, 0x1000);
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input_at ((to == REG) && (from == MEM), D32, source, 0x1000 - (text_sector_size + 4));
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input_by ((to == REG) && (from == IMM), size, source);
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input_at ((to == MEM) && (from == REG), D32, destination, 0x1000);
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input_at ((to == MEM) && (from == IMM), D32, destination, 0x1000);
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input_at ((to == MEM) && (from == REG), D32, destination, 0x1000 - (text_sector_size + 4));
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input_at ((to == MEM) && (from == IMM), D32, destination, 0x1000 - (text_sector_size + 4));
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input_by ((to == MEM) && (from == IMM), size, source);
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input_at ((to == REG) && (from == REL), D32, source, 0x4010b0);
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@ -259,7 +263,7 @@ static void build_enter (unsigned int dynamic_storage, unsigned int nesting_leve
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}
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static void build_in_out (unsigned int move, unsigned int size, unsigned int type, unsigned int port) {
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build_short_prefix (size == D16);
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short_prefix (size);
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input (1, 0xe4 + 0x01 * (size != D8) + 0x02 * (move != OUT) + 0x08 * (type == REG));
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@ -267,7 +271,7 @@ static void build_in_out (unsigned int move, unsigned int size, unsigned int typ
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}
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static void build_pop (unsigned int size, unsigned int to, unsigned int destination) {
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build_short_prefix (size == D16);
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short_prefix (size);
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input ((to == REG) && (upper (destination)), 0x41);
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@ -279,7 +283,7 @@ static void build_pop (unsigned int size, unsigned int to, unsigned int destinat
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}
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static void build_push (unsigned int size, unsigned int from, unsigned int source) {
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build_short_prefix (size == D16);
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short_prefix (size);
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input ((from == REG) && (upper (source)), 0x41);
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@ -295,7 +299,8 @@ static void build_push (unsigned int size, unsigned int from, unsigned int sourc
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static void build_float (unsigned int operation, unsigned int size, unsigned int from, unsigned int source) {
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input (from == MEM, 0xd8 + 0x04 * (size == D64));
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build_at (from == MEM, operation);
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modify_memory (operation, 0, from);
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input_at (from == MEM, size, source, 0);
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}
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@ -2,226 +2,36 @@
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#define ASSEMBLER_H
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enum {
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D8,
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D16,
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D32,
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D64
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D8, D16, D32, D64
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};
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enum {
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REL,
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REG,
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MEM,
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IMM
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REL, REG, MEM, IMM
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};
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enum {
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ASMDIRMEM,
|
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ASMDIRREL,
|
||||
ASMDIRIMM,
|
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ASMDIRREP,
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ADD,
|
||||
OR,
|
||||
ADC,
|
||||
SBB,
|
||||
AND,
|
||||
SUB,
|
||||
XOR,
|
||||
CMP,
|
||||
INC,
|
||||
DEC,
|
||||
NOT,
|
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NEG,
|
||||
MUL,
|
||||
IMUL,
|
||||
DIV,
|
||||
IDIV,
|
||||
NOP,
|
||||
RETN,
|
||||
RETF,
|
||||
LEAVE,
|
||||
LOCK,
|
||||
HLT,
|
||||
POPF,
|
||||
PUSHF,
|
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WAIT,
|
||||
CLC,
|
||||
CLD,
|
||||
CLI,
|
||||
STC,
|
||||
STD,
|
||||
STI,
|
||||
CMC,
|
||||
INSB,
|
||||
INSD,
|
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OUTSB,
|
||||
OUTSD,
|
||||
CDQ,
|
||||
CWDE,
|
||||
INAL,
|
||||
INEAX,
|
||||
INT3,
|
||||
IRETD,
|
||||
LODSB,
|
||||
LODSD,
|
||||
OUTAL,
|
||||
OUTEAX,
|
||||
SCASB,
|
||||
SCASD,
|
||||
STOSB,
|
||||
STOSD,
|
||||
SYSENTER,
|
||||
SYSEXIT,
|
||||
SYSCALL,
|
||||
SYSRET,
|
||||
PAUSE,
|
||||
CPUID,
|
||||
EMMS,
|
||||
RSM,
|
||||
FNOP,
|
||||
FCHS,
|
||||
FABS,
|
||||
FTST,
|
||||
FXAM,
|
||||
FLD1,
|
||||
FLDL2T,
|
||||
FLDL2E,
|
||||
FLDPI,
|
||||
FLDLG2,
|
||||
FLDLN2,
|
||||
FLDZ,
|
||||
F2XM1,
|
||||
FYL2X,
|
||||
FPTAN,
|
||||
FPATAN,
|
||||
FXTRACT,
|
||||
FPREM1,
|
||||
FDECSTP,
|
||||
FINCSTP,
|
||||
FPREM,
|
||||
FYL2XP1,
|
||||
FSQRT,
|
||||
FSINCOS,
|
||||
FRNDINT,
|
||||
FSCALE,
|
||||
FSIN,
|
||||
FCOS,
|
||||
INSW,
|
||||
OUTSW,
|
||||
CWD,
|
||||
CQO,
|
||||
CBW,
|
||||
CDQE,
|
||||
INVD,
|
||||
WBINVD,
|
||||
UD2,
|
||||
CLTS,
|
||||
INAX,
|
||||
IRETQ,
|
||||
LODSW,
|
||||
LODSQ,
|
||||
OUTAX,
|
||||
RDPMC,
|
||||
RDMSR,
|
||||
RDTSC,
|
||||
SCASW,
|
||||
SCASQ,
|
||||
STOSW,
|
||||
STOSQ,
|
||||
WRMSR,
|
||||
XLATB,
|
||||
ENTER,
|
||||
CALL,
|
||||
IN,
|
||||
OUT,
|
||||
JMP,
|
||||
JO,
|
||||
JNO,
|
||||
JB,
|
||||
JAE,
|
||||
JE,
|
||||
JNE,
|
||||
JBE,
|
||||
JA,
|
||||
JS,
|
||||
JNS,
|
||||
JPE,
|
||||
JPO,
|
||||
JL,
|
||||
JGE,
|
||||
JLE,
|
||||
JG,
|
||||
MOV,
|
||||
CMOVO,
|
||||
CMOVNO,
|
||||
CMOVB,
|
||||
CMOVAE,
|
||||
CMOVE,
|
||||
CMOVNE,
|
||||
CMOVBE,
|
||||
CMOVA,
|
||||
CMOVS,
|
||||
CMOVNS,
|
||||
CMOVPE,
|
||||
CMOVPO,
|
||||
CMOVL,
|
||||
CMOVGE,
|
||||
CMOVLE,
|
||||
CMOVG,
|
||||
PUSH,
|
||||
POP,
|
||||
BSWAP,
|
||||
TEST,
|
||||
RCL,
|
||||
RCR,
|
||||
ROL,
|
||||
ROR,
|
||||
SHL,
|
||||
SHR,
|
||||
SAL,
|
||||
SAR,
|
||||
REP,
|
||||
REPE,
|
||||
REPNE,
|
||||
REPZ,
|
||||
REPNZ,
|
||||
LOOP,
|
||||
LOOPE,
|
||||
LOOPNE,
|
||||
MOVBE,
|
||||
XADD,
|
||||
XCHG,
|
||||
LEA,
|
||||
POPCNT,
|
||||
BSF,
|
||||
BSR,
|
||||
FADD,
|
||||
FMUL,
|
||||
FCOM,
|
||||
FCOMP,
|
||||
FSUB,
|
||||
FSUBR,
|
||||
FDIV,
|
||||
FDIVR
|
||||
ASMDIRMEM, ASMDIRREL, ASMDIRIMM, ASMDIRREP,
|
||||
ADD, OR, ADC, SBB, AND, SUB, XOR, CMP,
|
||||
INC, DEC, NOT, NEG, MUL, IMUL, DIV, IDIV,
|
||||
FADD, FMUL, FCOM, FCOMP, FSUB, FSUBR, FDIV, FDIVR,
|
||||
NOP, RETN, RETF, LEAVE, POPF, PUSHF,
|
||||
SYSCALL, CPUID, FNOP, FCHS, FABS, FTST, FXAM, FLD1,
|
||||
FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, FLDZ, F2XM1, FYL2X,
|
||||
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1,
|
||||
FSQRT, FSINCOS, FRNDINT, FSCALE, FSIN, FCOS,
|
||||
ENTER, CALL, IN, OUT, JMP, MOV, POP, PUSH,
|
||||
JO, JNO, JB, JAE, JE, JNE, JBE, JA,
|
||||
JS, JNS, JPE, JPO, JL, JGE, JLE, JG,
|
||||
CMOVO, CMOVNO, CMOVB, CMOVAE, CMOVE, CMOVNE, CMOVBE, CMOVA,
|
||||
CMOVS, CMOVNS, CMOVPE, CMOVPO, CMOVL, CMOVGE, CMOVLE, CMOVG,
|
||||
BSWAP, TEST, XCHG, LEA, BSF, BSR,
|
||||
RCL, RCR, ROL, ROR, SHL, SHR, SAL, SAR,
|
||||
REP, REPE, REPNE, REPZ, REPNZ, LOOP, LOOPE, LOOPNE
|
||||
};
|
||||
|
||||
enum {
|
||||
GR0,
|
||||
GR1,
|
||||
GR2,
|
||||
GR3,
|
||||
GR4,
|
||||
GR5,
|
||||
GR6,
|
||||
GR7,
|
||||
GR8,
|
||||
GR9,
|
||||
GR10,
|
||||
GR11,
|
||||
GR12,
|
||||
GR13,
|
||||
GR14,
|
||||
GR15
|
||||
GR0, GR1, GR2, GR3, GR4, GR5, GR6, GR7,
|
||||
GR8, GR9, GR10, GR11, GR12, GR13, GR14, GR15
|
||||
};
|
||||
|
||||
extern unsigned int text_entry_point;
|
||||
|
||||
@ -155,22 +155,10 @@ nop { return INOP; }
|
||||
adc { return ITADC; }
|
||||
add { return ITADD; }
|
||||
and { return ITAND; }
|
||||
cbw { return ITCBW; }
|
||||
cdq { return ITCDQ; }
|
||||
cdqe { return ITCDQE; }
|
||||
clc { return ITCLC; }
|
||||
cld { return ITCLD; }
|
||||
cli { return ITCLI; }
|
||||
clts { return ITCLTS; }
|
||||
cmc { return ITCMC; }
|
||||
cmp { return ITCMP; }
|
||||
cpuid { return ITCPUID; }
|
||||
cqo { return ITCQO; }
|
||||
cwd { return ITCWD; }
|
||||
cwde { return ITCWDE; }
|
||||
dec { return ITDEC; }
|
||||
div { return ITDIV; }
|
||||
emms { return ITEMMS; }
|
||||
f2xm1 { return ITF2XM1; }
|
||||
fabs { return ITFABS; }
|
||||
fchs { return ITFCHS; }
|
||||
@ -199,74 +187,27 @@ fxam { return ITFXAM; }
|
||||
fxtract { return ITFXTRACT; }
|
||||
fyl2x { return ITFYL2X; }
|
||||
fyl2xp1 { return ITFYL2XP1; }
|
||||
hlt { return ITHLT; }
|
||||
idiv { return ITIDIV; }
|
||||
imul { return ITIMUL; }
|
||||
inal { return ITINAL; }
|
||||
inax { return ITINAX; }
|
||||
inc { return ITINC; }
|
||||
ineax { return ITINEAX; }
|
||||
insb { return ITINSB; }
|
||||
insd { return ITINSD; }
|
||||
insw { return ITINSW; }
|
||||
int3 { return ITINT3; }
|
||||
invd { return ITINVD; }
|
||||
iretd { return ITIRETD; }
|
||||
iretq { return ITIRETQ; }
|
||||
je { return ITJE; }
|
||||
jmp { return ITJMP; }
|
||||
jne { return ITJNE; }
|
||||
leave { return ITLEAVE; }
|
||||
lock { return ITLOCK; }
|
||||
lodsb { return ITLODSB; }
|
||||
lodsd { return ITLODSD; }
|
||||
lodsq { return ITLODSQ; }
|
||||
lodsw { return ITLODSW; }
|
||||
mov { return ITMOV; }
|
||||
mul { return ITMUL; }
|
||||
neg { return ITNEG; }
|
||||
nop { return ITNOP; }
|
||||
not { return ITNOT; }
|
||||
or { return ITOR; }
|
||||
outal { return ITOUTAL; }
|
||||
outax { return ITOUTAX; }
|
||||
outeax { return ITOUTEAX; }
|
||||
outsb { return ITOUTSB; }
|
||||
outsd { return ITOUTSD; }
|
||||
outsw { return ITOUTSW; }
|
||||
pause { return ITPAUSE; }
|
||||
pop { return ITPOP; }
|
||||
popf { return ITPOPF; }
|
||||
pushf { return ITPUSHF; }
|
||||
rdmsr { return ITRDMSR; }
|
||||
rdpmc { return ITRDPMC; }
|
||||
rdtsc { return ITRDTSC; }
|
||||
retf { return ITRETF; }
|
||||
retn { return ITRETN; }
|
||||
rsm { return ITRSM; }
|
||||
sar { return ITSAR; }
|
||||
sbb { return ITSBB; }
|
||||
scasb { return ITSCASB; }
|
||||
scasd { return ITSCASD; }
|
||||
scasq { return ITSCASQ; }
|
||||
scasw { return ITSCASW; }
|
||||
stc { return ITSTC; }
|
||||
std { return ITSTD; }
|
||||
sti { return ITSTI; }
|
||||
stosb { return ITSTOSB; }
|
||||
stosd { return ITSTOSD; }
|
||||
stosq { return ITSTOSQ; }
|
||||
stosw { return ITSTOSW; }
|
||||
sub { return ITSUB; }
|
||||
syscall { return ITSYSCALL; }
|
||||
sysenter { return ITSYSENTER; }
|
||||
sysexit { return ITSYSEXIT; }
|
||||
sysret { return ITSYSRET; }
|
||||
ud2 { return ITUD2; }
|
||||
wait { return ITWAIT; }
|
||||
wbinvd { return ITWBINVD; }
|
||||
wrmsr { return ITWRMSR; }
|
||||
xlatb { return ITXLATB; }
|
||||
xor { return ITXOR; }
|
||||
|
||||
/* #placeholder<instruction_scanner_instructions> END
|
||||
|
||||
@ -93,7 +93,7 @@
|
||||
// Instructions
|
||||
%token INOP
|
||||
// #placeholder<instruction_token_list> BEGIN
|
||||
%token ITADC ITADD ITAND ITCBW ITCDQ ITCDQE ITCLC ITCLD ITCLI ITCLTS ITCMC ITCMP ITCPUID ITCQO ITCWD ITCWDE ITDEC ITDIV ITEMMS ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITHLT ITIDIV ITIMUL ITINAL ITINAX ITINC ITINEAX ITINSB ITINSD ITINSW ITINT3 ITINVD ITIRETD ITIRETQ ITJE ITJMP ITJNE ITLEAVE ITLOCK ITLODSB ITLODSD ITLODSQ ITLODSW ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITOUTAL ITOUTAX ITOUTEAX ITOUTSB ITOUTSD ITOUTSW ITPAUSE ITPOP ITPOPF ITPUSHF ITRDMSR ITRDPMC ITRDTSC ITRETF ITRETN ITRSM ITSAR ITSBB ITSCASB ITSCASD ITSCASQ ITSCASW ITSTC ITSTD ITSTI ITSTOSB ITSTOSD ITSTOSQ ITSTOSW ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITUD2 ITWAIT ITWBINVD ITWRMSR ITXLATB ITXOR
|
||||
%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSHF ITRETF ITRETN ITSBB ITSUB ITSYSCALL ITXOR
|
||||
// #placeholder<instruction_token_list> END
|
||||
|
||||
// Instruction-likes
|
||||
@ -438,44 +438,10 @@ instruction: INOP { append_instructions(NOP); }
|
||||
| ITRETN { append_instructions(RETN); }
|
||||
| ITRETF { append_instructions(RETF); }
|
||||
| ITLEAVE { append_instructions(LEAVE); }
|
||||
| ITLOCK { append_instructions(LOCK); }
|
||||
| ITHLT { append_instructions(HLT); }
|
||||
| ITPOPF { append_instructions(POPF); }
|
||||
| ITPUSHF { append_instructions(PUSHF); }
|
||||
| ITWAIT { append_instructions(WAIT); }
|
||||
| ITCLC { append_instructions(CLC); }
|
||||
| ITCLD { append_instructions(CLD); }
|
||||
| ITCLI { append_instructions(CLI); }
|
||||
| ITSTC { append_instructions(STC); }
|
||||
| ITSTD { append_instructions(STD); }
|
||||
| ITSTI { append_instructions(STI); }
|
||||
| ITCMC { append_instructions(CMC); }
|
||||
| ITINSB { append_instructions(INSB); }
|
||||
| ITINSD { append_instructions(INSD); }
|
||||
| ITOUTSB { append_instructions(OUTSB); }
|
||||
| ITOUTSD { append_instructions(OUTSD); }
|
||||
| ITCDQ { append_instructions(CDQ); }
|
||||
| ITCWDE { append_instructions(CWDE); }
|
||||
| ITINAL { append_instructions(INAL); }
|
||||
| ITINEAX { append_instructions(INEAX); }
|
||||
| ITINT3 { append_instructions(INT3); }
|
||||
| ITIRETD { append_instructions(IRETD); }
|
||||
| ITLODSB { append_instructions(LODSB); }
|
||||
| ITLODSD { append_instructions(LODSD); }
|
||||
| ITOUTAL { append_instructions(OUTAL); }
|
||||
| ITOUTEAX { append_instructions(OUTEAX); }
|
||||
| ITSCASB { append_instructions(SCASB); }
|
||||
| ITSCASD { append_instructions(SCASD); }
|
||||
| ITSTOSB { append_instructions(STOSB); }
|
||||
| ITSTOSD { append_instructions(STOSD); }
|
||||
| ITSYSENTER { append_instructions(SYSENTER); }
|
||||
| ITSYSEXIT { append_instructions(SYSEXIT); }
|
||||
| ITSYSCALL { append_instructions(SYSCALL); }
|
||||
| ITSYSRET { append_instructions(SYSRET); }
|
||||
| ITPAUSE { append_instructions(PAUSE); }
|
||||
| ITCPUID { append_instructions(CPUID); }
|
||||
| ITEMMS { append_instructions(EMMS); }
|
||||
| ITRSM { append_instructions(RSM); }
|
||||
| ITFNOP { append_instructions(FNOP); }
|
||||
| ITFCHS { append_instructions(FCHS); }
|
||||
| ITFABS { append_instructions(FABS); }
|
||||
@ -504,30 +470,6 @@ instruction: INOP { append_instructions(NOP); }
|
||||
| ITFSCALE { append_instructions(FSCALE); }
|
||||
| ITFSIN { append_instructions(FSIN); }
|
||||
| ITFCOS { append_instructions(FCOS); }
|
||||
| ITINSW { append_instructions(INSW); }
|
||||
| ITOUTSW { append_instructions(OUTSW); }
|
||||
| ITCWD { append_instructions(CWD); }
|
||||
| ITCQO { append_instructions(CQO); }
|
||||
| ITCBW { append_instructions(CBW); }
|
||||
| ITCDQE { append_instructions(CDQE); }
|
||||
| ITINVD { append_instructions(INVD); }
|
||||
| ITWBINVD { append_instructions(WBINVD); }
|
||||
| ITUD2 { append_instructions(UD2); }
|
||||
| ITCLTS { append_instructions(CLTS); }
|
||||
| ITINAX { append_instructions(INAX); }
|
||||
| ITIRETQ { append_instructions(IRETQ); }
|
||||
| ITLODSW { append_instructions(LODSW); }
|
||||
| ITLODSQ { append_instructions(LODSQ); }
|
||||
| ITOUTAX { append_instructions(OUTAX); }
|
||||
| ITRDPMC { append_instructions(RDPMC); }
|
||||
| ITRDMSR { append_instructions(RDMSR); }
|
||||
| ITRDTSC { append_instructions(RDTSC); }
|
||||
| ITSCASW { append_instructions(SCASW); }
|
||||
| ITSCASQ { append_instructions(SCASQ); }
|
||||
| ITSTOSW { append_instructions(STOSW); }
|
||||
| ITSTOSQ { append_instructions(STOSQ); }
|
||||
| ITWRMSR { append_instructions(WRMSR); }
|
||||
| ITXLATB { append_instructions(XLATB); }
|
||||
| ITJMP relative { append_instructions( JMP, D32, REL, $2 ); }
|
||||
| ITJE relative { append_instructions( JE, D32, REL, $2 ); }
|
||||
| ITJNE relative { append_instructions( JNE, D32, REL, $2 ); }
|
||||
@ -553,16 +495,46 @@ instruction: INOP { append_instructions(NOP); }
|
||||
| ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITSBB register register { append_instructions( SBB, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITAND register register { append_instructions( AND, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITADD register immediate { append_instructions( ADD, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITOR register immediate { append_instructions( OR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITADC register immediate { append_instructions( ADC, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITSBB register immediate { append_instructions( SBB, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITSUB register immediate { append_instructions( SUB, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITXOR register immediate { append_instructions( XOR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITCMP register immediate { append_instructions( CMP, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITADD register memory { append_instructions( ADD, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITOR register memory { append_instructions( OR, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITADC register memory { append_instructions( ADC, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITSBB register memory { append_instructions( SBB, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITAND register memory { append_instructions( AND, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITSUB register memory { append_instructions( SUB, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITXOR register memory { append_instructions( XOR, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITCMP register memory { append_instructions( CMP, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITADD memory register { append_instructions( ADD, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITOR memory register { append_instructions( OR, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITADC memory register { append_instructions( ADC, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITSBB memory register { append_instructions( SBB, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITAND memory register { append_instructions( AND, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITSUB memory register { append_instructions( SUB, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITXOR memory register { append_instructions( XOR, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITCMP memory register { append_instructions( CMP, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITADD memory immediate { append_instructions( ADD, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITOR memory immediate { append_instructions( OR, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITADC memory immediate { append_instructions( ADC, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITSBB memory immediate { append_instructions( SBB, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITAND memory immediate { append_instructions( AND, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITSUB memory immediate { append_instructions( SUB, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITXOR memory immediate { append_instructions( XOR, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITCMP memory immediate { append_instructions( CMP, D32, MEM, $2, $3.type, $3.value ); }
|
||||
| ITMOV register register { append_instructions( MOV, $2.size, REG, $2.number, REG, $3.number ); }
|
||||
| ITMOV register immediate { append_instructions( MOV, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITMOV register memory { append_instructions( MOV, $2.size, REG, $2.number, MEM, $3 ); }
|
||||
| ITMOV memory register { append_instructions( MOV, D32, MEM, $2, REG, $3.number ); }
|
||||
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
||||
| ITMOV memory immediate { append_instructions( MOV, D32, MEM, $2, $3.type, $3.value ); }
|
||||
|
||||
// #placeholder<instruction_parser_rules> END
|
||||
;
|
||||
|
||||
84
test/game_of_life.asm
Normal file
84
test/game_of_life.asm
Normal file
@ -0,0 +1,84 @@
|
||||
format ELF64 executable 3
|
||||
|
||||
segment readable executable
|
||||
|
||||
entry main
|
||||
|
||||
char: nop
|
||||
nop
|
||||
mov eax, 1
|
||||
nop
|
||||
mov edi, 1
|
||||
nop
|
||||
mov edx, 1
|
||||
nop
|
||||
syscall
|
||||
ret
|
||||
|
||||
main: nop
|
||||
main_loop:
|
||||
nop
|
||||
mov dword[y], 0
|
||||
begin_loop_y:
|
||||
nop
|
||||
cmp dword[y], 8
|
||||
nop
|
||||
je end_loop_y
|
||||
nop
|
||||
mov dword[x], 0
|
||||
begin_loop_x:
|
||||
nop
|
||||
cmp dword[x], 8
|
||||
nop
|
||||
je end_loop_x
|
||||
nop
|
||||
mov esi, c
|
||||
nop
|
||||
call char
|
||||
nop
|
||||
inc dword[x]
|
||||
nop
|
||||
jmp begin_loop_x
|
||||
end_loop_x:
|
||||
nop
|
||||
mov esi, c
|
||||
nop
|
||||
add esi, 2
|
||||
nop
|
||||
call char
|
||||
nop
|
||||
inc dword[y]
|
||||
nop
|
||||
jmp begin_loop_y
|
||||
end_loop_y:
|
||||
nop
|
||||
mov esi, c
|
||||
nop
|
||||
add esi, 3
|
||||
nop
|
||||
call char
|
||||
nop
|
||||
inc esi
|
||||
nop
|
||||
call char
|
||||
nop
|
||||
inc esi
|
||||
nop
|
||||
call char
|
||||
nop
|
||||
jmp main_loop
|
||||
nop
|
||||
mov eax, 60
|
||||
mov edi, 0
|
||||
syscall
|
||||
|
||||
segment readable writable
|
||||
|
||||
y: dd 0
|
||||
x: dd 0
|
||||
p: dd 0
|
||||
q: dd 0
|
||||
f: db "..#.....#.#.......##............................................"
|
||||
c: db ".#", 10, 27, "[H"
|
||||
n: dd 0
|
||||
b: db "..#.....#.#.......##............................................"
|
||||
70
test/game_of_life.eax
Normal file
70
test/game_of_life.eax
Normal file
@ -0,0 +1,70 @@
|
||||
fast procedure char
|
||||
begin nop
|
||||
nop mov eax 1 nop mov edi 1 nop mov edx 1 nop syscall
|
||||
end procedure
|
||||
|
||||
unix program main
|
||||
s8 <> f = "..#.....#.#.......##............................................"
|
||||
s8 <> b = "..#.....#.#.......##............................................"
|
||||
s8 <> c = ".#\n\e[H"
|
||||
s32 y = 0
|
||||
s32 x = 0
|
||||
s32 p = 0
|
||||
s32 q = 0
|
||||
s32 n = 0
|
||||
begin nop
|
||||
main_loop:
|
||||
nop mov [y] 0
|
||||
begin_loop_y:
|
||||
nop cmp [y] 8
|
||||
nop je end_loop_y
|
||||
nop mov [x] 0
|
||||
begin_loop_x:
|
||||
nop cmp [x] 8
|
||||
nop je end_loop_x
|
||||
nop mov esi c
|
||||
nop fastcall char
|
||||
nop inc [x]
|
||||
nop jmp begin_loop_x
|
||||
end_loop_x:
|
||||
nop mov esi c
|
||||
nop add esi 2
|
||||
nop fastcall char
|
||||
nop inc [y]
|
||||
nop jmp begin_loop_y
|
||||
end_loop_y:
|
||||
nop mov esi c
|
||||
nop add esi 3
|
||||
nop fastcall char
|
||||
nop inc esi
|
||||
nop fastcall char
|
||||
nop inc esi
|
||||
nop fastcall char
|
||||
nop jmp main_loop
|
||||
nop exit 0
|
||||
end program
|
||||
/*
|
||||
x,y,p,q,f[12][24],b[12][24],n;
|
||||
|
||||
main(){
|
||||
f[0][1]=f[1][2]=f[2][0]=f[2][1]=f[2][2]=1;
|
||||
l:
|
||||
for(y=0;y<12;++y){
|
||||
for(x=0;x<24;++x){
|
||||
n=0;
|
||||
for(q=-1;q<2;++q)
|
||||
for(p=-1;p<2;++p)
|
||||
if(p!=0||q!=0)
|
||||
if(f[((y+q)%12+12)%12][((x+p)%24+24)%24])
|
||||
n+=1;
|
||||
b[y][x]=f[y][x]?(n==2||n==3):n==3;
|
||||
printf("%c",".#"[f[y][x]]);
|
||||
}
|
||||
printf("\012");
|
||||
}
|
||||
printf("\033[H");
|
||||
memcpy(f,b,1152);
|
||||
usleep(100000);
|
||||
goto l;
|
||||
}
|
||||
*/
|
||||
15
test/india.eax
Normal file
15
test/india.eax
Normal file
@ -0,0 +1,15 @@
|
||||
unix program hello
|
||||
s8 <> message = "Hello, world!"
|
||||
begin
|
||||
mov ebx 0
|
||||
mov edi 1
|
||||
mov esi message
|
||||
mov edx 13
|
||||
india:
|
||||
mov eax 1
|
||||
syscall
|
||||
inc ebx
|
||||
cmp ebx 1000000
|
||||
jne india
|
||||
exit 0
|
||||
end program
|
||||
@ -3,44 +3,10 @@ set instructions {
|
||||
{retn}
|
||||
{retf}
|
||||
{leave}
|
||||
{lock}
|
||||
{hlt}
|
||||
{popf}
|
||||
{pushf}
|
||||
{wait}
|
||||
{clc}
|
||||
{cld}
|
||||
{cli}
|
||||
{stc}
|
||||
{std}
|
||||
{sti}
|
||||
{cmc}
|
||||
{insb}
|
||||
{insd}
|
||||
{outsb}
|
||||
{outsd}
|
||||
{cdq}
|
||||
{cwde}
|
||||
{inal}
|
||||
{ineax}
|
||||
{int3}
|
||||
{iretd}
|
||||
{lodsb}
|
||||
{lodsd}
|
||||
{outal}
|
||||
{outeax}
|
||||
{scasb}
|
||||
{scasd}
|
||||
{stosb}
|
||||
{stosd}
|
||||
{sysenter}
|
||||
{sysexit}
|
||||
{syscall}
|
||||
{sysret}
|
||||
{pause}
|
||||
{cpuid}
|
||||
{emms}
|
||||
{rsm}
|
||||
{fnop}
|
||||
{fchs}
|
||||
{fabs}
|
||||
@ -69,30 +35,6 @@ set instructions {
|
||||
{fscale}
|
||||
{fsin}
|
||||
{fcos}
|
||||
{insw}
|
||||
{outsw}
|
||||
{cwd}
|
||||
{cqo}
|
||||
{cbw}
|
||||
{cdqe}
|
||||
{invd}
|
||||
{wbinvd}
|
||||
{ud2}
|
||||
{clts}
|
||||
{inax}
|
||||
{iretq}
|
||||
{lodsw}
|
||||
{lodsq}
|
||||
{outax}
|
||||
{rdpmc}
|
||||
{rdmsr}
|
||||
{rdtsc}
|
||||
{scasw}
|
||||
{scasq}
|
||||
{stosw}
|
||||
{stosq}
|
||||
{wrmsr}
|
||||
{xlatb}
|
||||
{jmp relative}
|
||||
{je relative}
|
||||
{jne relative}
|
||||
@ -118,16 +60,46 @@ set instructions {
|
||||
{adc register register}
|
||||
{sbb register register}
|
||||
{and register register}
|
||||
{and register immediate}
|
||||
{sub register register}
|
||||
{xor register register}
|
||||
{cmp register register}
|
||||
{add register immediate}
|
||||
{or register immediate}
|
||||
{adc register immediate}
|
||||
{sbb register immediate}
|
||||
{and register immediate}
|
||||
{sub register immediate}
|
||||
{xor register immediate}
|
||||
{cmp register immediate}
|
||||
{add register memory}
|
||||
{or register memory}
|
||||
{adc register memory}
|
||||
{sbb register memory}
|
||||
{and register memory}
|
||||
{sub register memory}
|
||||
{xor register memory}
|
||||
{cmp register memory}
|
||||
{add memory register}
|
||||
{or memory register}
|
||||
{adc memory register}
|
||||
{sbb memory register}
|
||||
{and memory register}
|
||||
{sub memory register}
|
||||
{xor memory register}
|
||||
{cmp memory register}
|
||||
{add memory immediate}
|
||||
{or memory immediate}
|
||||
{adc memory immediate}
|
||||
{sbb memory immediate}
|
||||
{and memory immediate}
|
||||
{sub memory immediate}
|
||||
{xor memory immediate}
|
||||
{cmp memory immediate}
|
||||
{mov register register}
|
||||
{mov register immediate}
|
||||
{mov register memory}
|
||||
{mov memory register}
|
||||
{sar register immediate}
|
||||
{mov memory immediate}
|
||||
}
|
||||
|
||||
proc malformed_instruction {i} {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user