608 lines
21 KiB
Plaintext
608 lines
21 KiB
Plaintext
/* EAXHLA parser
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* This source file has minimal knowledge about highlevel constructs.
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* The only time it interacts with the assembler interface directly is when
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* instructions are encountered or processing a machine code block,
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* everything else is delegated to eaxhla.c
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*/
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%code requires {
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#include "eaxhla.h"
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}
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%{
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#include <stdio.h>
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#include <math.h>
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#include <stdbool.h>
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#include "eaxhla.h"
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#include "eaxhla.yy.h"
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#include "assembler.h"
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#include "compile.h"
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#include "debug.h"
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extern void yyfree_leftovers(void);
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extern char * yyfilename;
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void yyerror(const char * errmsg) {
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issue_error("%s near \033[1m'%s'\033[0m", errmsg, yytext);
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}
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%}
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%union{
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long intval;
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char * strval;
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struct {
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int type;
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int value;
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} argval;
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struct {
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unsigned long long len;
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void * data;
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} blobval;
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symbol_t varval;
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cpuregister_t regval;
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}
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%token MYBEGIN
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%token PROGRAM END_PROGRAM
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%token PROCEDURE END_PROCEDURE
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%token REPEAT END_REPEAT
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%token IF THEN ELSE END_IF
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%token MACHINE END_MACHINE
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%token LIBRARY END_LIBRARY
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%token UNTIL
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%token<strval> IDENTIFIER LABEL
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%type<argval> immediate
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%type<intval> memory dereference relative
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%type<intval> artimetric_block artimetric_expression artimetric_operand
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%type<intval> value
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%token<intval> LITERAL
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%token<blobval> ARRAY_LITERAL
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// Specifiers
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%token FAST
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%token UNIX WIN64 SHELL
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// Logic
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%token ITNEQ
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/*
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%token ITOR ITXOR ITAND ITNOT // these are (in)conveniently instructions too
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*/
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// Type info
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%token TIN
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%token S8 S16 S32 S64
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%token U8 U16 U32 U64
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%type<intval> type
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%type<varval> declaration
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%type<varval> stored_literal
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// Registers
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%type<regval> register register64s register32s register16s register8s
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// #placeholder<register_token_list> BEGIN
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%token RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15
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%token EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D
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%token AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W
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%token AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B
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// #placeholder<register_token_list> END
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// Instructions
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%token INOP
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// #placeholder<instruction_token_list> BEGIN
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%token ITADC ITADD ITAND ITCMP ITCPUID ITDEC ITDIV ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITLOOP ITLOOPE ITLOOPNE ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITPOP ITPOPF ITPUSH ITPUSHF ITRCL ITRCR ITRETF ITRETN ITROL ITROR ITSAL ITSAR ITSBB ITSHL ITSHR ITSUB ITSYSCALL ITXOR
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// #placeholder<instruction_token_list> END
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// Instruction-likes
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%token FASTCALL
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%token EXIT BREAK CONTINUE
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%%
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document: hla { fin_hla(); }
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;
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hla: %empty
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// | library hla
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| program hla
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| function hla
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;
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program: program_head declaration_section MYBEGIN code END_PROGRAM {
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}
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;
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program_head: program_specifier PROGRAM IDENTIFIER {
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add_scope($3);
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add_program($3);
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free($3);
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};
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program_specifier: %empty
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| system_specifier
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;
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system_specifier
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: UNIX { system_type = UNIX; }
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| WIN64 { system_type = WIN64; }
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| SHELL { system_type = SHELL; }
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;
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// XXX: end procedure thing
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function: function_head declaration_section MYBEGIN code END_PROCEDURE {
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fin_procedure();
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}
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;
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function_head: function_specifier PROCEDURE IDENTIFIER {
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add_scope($3);
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add_procedure($3);
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free($3);
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}
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;
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function_specifier: %empty
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| FAST
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;
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declaration_section: %empty
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| declaration declaration_section
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| error declaration_section { yyerrok; }
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;
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declaration:
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variable_specifier type IDENTIFIER {
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add_variable($2, $3);
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free($3);
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}
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| variable_specifier type IDENTIFIER '=' LITERAL {
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add_variable_with_value($2, $3, $5);
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free($3);
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}
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| variable_specifier type '<' value '>' IDENTIFIER {
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add_array_variable($2, $6, $4);
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free($6);
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}
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| variable_specifier type '<' value '>' IDENTIFIER '=' ARRAY_LITERAL {
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add_array_variable_with_value($2, $6, $4, $8.data, $8.len);
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free($6);
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}
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| variable_specifier type '<' '>' IDENTIFIER '=' ARRAY_LITERAL {
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add_array_variable_with_value($2, $5, $7.len, $7.data, $7.len);
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free($5);
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}
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;
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variable_specifier: %empty
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| TIN
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;
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type: S8 { $$ = S8; }
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| S16 { $$ = S16; }
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| S32 { $$ = S32; }
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| S64 { $$ = S64; }
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| U8 { $$ = U8; }
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| U16 { $$ = U16; }
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| U32 { $$ = U32; }
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| U64 { $$ = U64; }
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;
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immediate: LITERAL {
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$$.type = IMM;
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$$.value = $1;
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}
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| IDENTIFIER {
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symbol_t * variable = get_variable($1);
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$$.type = REL;
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$$.value = variable->_id;
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free($1);
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}
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/*
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| stored_literal {
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$$.type = REL;
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$$.value = $1
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}
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*/
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;
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memory: artimetric_block
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| dereference
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;
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dereference: '[' IDENTIFIER ']' {
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$$ = get_variable($2)->_id;
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free($2);
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}
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| '[' IDENTIFIER '+' value ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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| '[' IDENTIFIER '-' value ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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;
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relative: IDENTIFIER {
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$$ = get_relative($1)->_id;
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free($1);
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}
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;
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value: artimetric_block
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| LITERAL
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| IDENTIFIER {
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symbol_t * var = get_variable($1);
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$$ = var->value;
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free($1);
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}
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;
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stored_literal: ARRAY_LITERAL {
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add_literal($1.data, $1.len);
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}
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;
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code: %empty
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| error code { /*yyerrok;*/ }
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| repeat code
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| if code
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| call code
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| label code
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| machine code
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| instruction code
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| instruction_like code
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;
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label: LABEL {
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add_label($1, true);
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free($1);
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}
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;
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repeat_start: REPEAT {
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add_repeat();
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}
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;
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repeat_end: END_REPEAT {
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fin_repeat();
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}
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;
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repeat: repeat_start code repeat_end
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/*| UNTIL logic REPEAT code END_REPEAT*/
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;
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if_start: IF { add_if(); }
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;
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if_end: END_IF { fin_if(); }
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;
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if: if_start logic THEN code if_end
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| if_start logic THEN code ELSE code if_end
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;
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logic: register '=' register {
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add_logic(&$1, &$3, EQUALS);
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}
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| register '!' '=' register {
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add_logic(&$1, &$4, GREATER_THAN);
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}
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| register '<' register {
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add_logic(&$1, &$3, LESSER_THAN);
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}
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| register '>' register {
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add_logic(&$1, &$3, GREATER_THAN);
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}
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;
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/*
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logical_operand ITAND logical_operand
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| logical_operand ITOR logical_operand
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| logical_operand ITXOR logical_operand
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| logical_operand '=' logical_operand
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| logical_operand ITNEQ logical_operand
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| sublogic
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| ITNOT logic
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;
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logical_operand: sublogic
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| register
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| artimetric_block
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| dereference
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| LITERAL
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| IDENTIFIER
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;
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sublogic: '(' logic ')'
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;
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*/
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machine: MACHINE machine_code END_MACHINE
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;
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machine_code: %empty
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| machine_code LITERAL {
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append_instructions(ASMDIRIMM, D8, 1, $2);
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}
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| machine_code ARRAY_LITERAL {
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append_instructions(ASMDIRIMM, D8, $2.len);
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for (unsigned long long i = 0; i < $2.len; i++) {
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append_instructions(((char*)$2.data)[i]);
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}
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}
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| machine_code IDENTIFIER { free($2); }
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;
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call: FASTCALL IDENTIFIER arguments {
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add_fastcall($2);
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free($2);
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}
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;
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arguments: %empty
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| IDENTIFIER arguments { free($1); }
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| LITERAL arguments
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| register arguments
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| artimetric_block arguments
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| stored_literal arguments
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;
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register: register64s { $$ = $1; $$.size = D64; }
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| register32s { $$ = $1; $$.size = D32; }
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| register16s { $$ = $1; $$.size = D16; }
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| register8s { $$ = $1; $$.size = D8; }
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;
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// #placeholder<register_parser_rules> BEGIN
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register64s: RAX { $$.number = GR0; }
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| RCX { $$.number = GR1; }
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| RDX { $$.number = GR2; }
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| RBX { $$.number = GR3; }
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| RSP { $$.number = GR4; }
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| RBP { $$.number = GR5; }
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| RSI { $$.number = GR6; }
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| RDI { $$.number = GR7; }
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| R8 { $$.number = GR8; }
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| R9 { $$.number = GR9; }
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| R10 { $$.number = GR10; }
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| R11 { $$.number = GR11; }
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| R12 { $$.number = GR12; }
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| R13 { $$.number = GR13; }
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| R14 { $$.number = GR14; }
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| R15 { $$.number = GR15; }
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;
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register32s: EAX { $$.number = GR0; }
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| ECX { $$.number = GR1; }
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| EDX { $$.number = GR2; }
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| EBX { $$.number = GR3; }
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| ESP { $$.number = GR4; }
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| EBP { $$.number = GR5; }
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| ESI { $$.number = GR6; }
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| EDI { $$.number = GR7; }
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| R8D { $$.number = GR8; }
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| R9D { $$.number = GR9; }
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| R10D { $$.number = GR10; }
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| R11D { $$.number = GR11; }
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| R12D { $$.number = GR12; }
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| R13D { $$.number = GR13; }
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| R14D { $$.number = GR14; }
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| R15D { $$.number = GR15; }
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;
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register16s: AX { $$.number = GR0; }
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| CX { $$.number = GR1; }
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| DX { $$.number = GR2; }
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| BX { $$.number = GR3; }
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| SP { $$.number = GR4; }
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| BP { $$.number = GR5; }
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| SI { $$.number = GR6; }
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| DI { $$.number = GR7; }
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| R8W { $$.number = GR8; }
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| R9W { $$.number = GR9; }
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| R10W { $$.number = GR10; }
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| R11W { $$.number = GR11; }
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| R12W { $$.number = GR12; }
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| R13W { $$.number = GR13; }
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| R14W { $$.number = GR14; }
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| R15W { $$.number = GR15; }
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;
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register8s: AL { $$.number = GR0; }
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| CL { $$.number = GR1; }
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| DL { $$.number = GR2; }
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| BL { $$.number = GR3; }
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| SPL { $$.number = GR4; }
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| BPL { $$.number = GR5; }
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| SIL { $$.number = GR6; }
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| DIL { $$.number = GR7; }
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| R8B { $$.number = GR8; }
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| R9B { $$.number = GR9; }
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| R10B { $$.number = GR10; }
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| R11B { $$.number = GR11; }
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| R12B { $$.number = GR12; }
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| R13B { $$.number = GR13; }
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| R14B { $$.number = GR14; }
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| R15B { $$.number = GR15; }
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;
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// #placeholder<register_parser_rules> END
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artimetric_block: '{' artimetric_expression '}' { $$ = $2; }
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;
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artimetric_expression: %empty { $$ = 0; }
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| artimetric_operand
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| artimetric_expression '+' artimetric_operand { $$ = $1 + $3; }
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| artimetric_expression '-' artimetric_operand { $$ = $1 - $3; }
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| artimetric_expression '*' artimetric_operand { $$ = $1 * $3; }
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| artimetric_expression '/' artimetric_operand { $$ = $1 / $3; }
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| artimetric_expression '%' artimetric_operand { $$ = $1 % $3; }
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| artimetric_expression '^' artimetric_operand { $$ = pow($1, $3); }
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;
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artimetric_operand: LITERAL
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| IDENTIFIER {
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$$ = get_variable($1)->value;
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}
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;
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instruction_like: exit
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| continue
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| break
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;
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/* XXX: currently passing a negative is gramatically legal
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we could either define a more abstract token
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and only accept positives here or make eaxhla.c check.
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as of now however, i do not care
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*/
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continue: CONTINUE { add_continue(1); }
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| CONTINUE LITERAL { add_continue($2); }
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;
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break: BREAK { add_break(1); }
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| BREAK LITERAL { add_break($2); }
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;
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exit: EXIT value { append_exit($2); }
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;
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/* XXX
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library: LIBRARY declaration_section MYBEGIN library_code END_LIBRARY
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;
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library_code: %empty
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| function library_code
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;
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*/
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instruction: INOP { append_instructions(NOP); }
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// #placeholder<instruction_parser_rules> BEGIN
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| ITNOP { append_instructions(NOP); }
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| ITRETN { append_instructions(RETN); }
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| ITRETF { append_instructions(RETF); }
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| ITLEAVE { append_instructions(LEAVE); }
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| ITPOPF { append_instructions(POPF); }
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| ITPUSHF { append_instructions(PUSHF); }
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| ITSYSCALL { append_instructions(SYSCALL); }
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| ITCPUID { append_instructions(CPUID); }
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| ITFNOP { append_instructions(FNOP); }
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| ITFCHS { append_instructions(FCHS); }
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| ITFABS { append_instructions(FABS); }
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| ITFTST { append_instructions(FTST); }
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| ITFXAM { append_instructions(FXAM); }
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| ITFLD1 { append_instructions(FLD1); }
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| ITFLDL2T { append_instructions(FLDL2T); }
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| ITFLDL2E { append_instructions(FLDL2E); }
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| ITFLDPI { append_instructions(FLDPI); }
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| ITFLDLG2 { append_instructions(FLDLG2); }
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| ITFLDLN2 { append_instructions(FLDLN2); }
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| ITFLDZ { append_instructions(FLDZ); }
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| ITF2XM1 { append_instructions(F2XM1); }
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| ITFYL2X { append_instructions(FYL2X); }
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| ITFPTAN { append_instructions(FPTAN); }
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| ITFPATAN { append_instructions(FPATAN); }
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| ITFXTRACT { append_instructions(FXTRACT); }
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| ITFPREM1 { append_instructions(FPREM1); }
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| ITFDECSTP { append_instructions(FDECSTP); }
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| ITFINCSTP { append_instructions(FINCSTP); }
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| ITFPREM { append_instructions(FPREM); }
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| ITFYL2XP1 { append_instructions(FYL2XP1); }
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| ITFSQRT { append_instructions(FSQRT); }
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| ITFSINCOS { append_instructions(FSINCOS); }
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| ITFRNDINT { append_instructions(FRNDINT); }
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| ITFSCALE { append_instructions(FSCALE); }
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| ITFSIN { append_instructions(FSIN); }
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| ITFCOS { append_instructions(FCOS); }
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|
| ITJMP relative { append_instructions( JMP, D32, REL, $2 ); }
|
|
| ITJE relative { append_instructions( JE, D32, REL, $2 ); }
|
|
| ITJNE relative { append_instructions( JNE, D32, REL, $2 ); }
|
|
| ITINC register { append_instructions( INC, $2.size, REG, $2.number ); }
|
|
| ITDEC register { append_instructions( DEC, $2.size, REG, $2.number ); }
|
|
| ITNOT register { append_instructions( NOT, $2.size, REG, $2.number ); }
|
|
| ITNEG register { append_instructions( NEG, $2.size, REG, $2.number ); }
|
|
| ITMUL register { append_instructions( MUL, $2.size, REG, $2.number ); }
|
|
| ITIMUL register { append_instructions( IMUL, $2.size, REG, $2.number ); }
|
|
| ITDIV register { append_instructions( DIV, $2.size, REG, $2.number ); }
|
|
| ITIDIV register { append_instructions( IDIV, $2.size, REG, $2.number ); }
|
|
| ITPOP register { append_instructions( POP, $2.size, REG, $2.number ); }
|
|
| ITINC memory { append_instructions( INC, D32, MEM, $2 ); }
|
|
| ITDEC memory { append_instructions( DEC, D32, MEM, $2 ); }
|
|
| ITNOT memory { append_instructions( NOT, D32, MEM, $2 ); }
|
|
| ITNEG memory { append_instructions( NEG, D32, MEM, $2 ); }
|
|
| ITMUL memory { append_instructions( MUL, D32, MEM, $2 ); }
|
|
| ITIMUL memory { append_instructions( IMUL, D32, MEM, $2 ); }
|
|
| ITDIV memory { append_instructions( DIV, D32, MEM, $2 ); }
|
|
| ITIDIV memory { append_instructions( IDIV, D32, MEM, $2 ); }
|
|
| ITADD register register { append_instructions( ADD, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITOR register register { append_instructions( OR, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITSBB register register { append_instructions( SBB, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITAND register register { append_instructions( AND, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITADD register immediate { append_instructions( ADD, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITOR register immediate { append_instructions( OR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITADC register immediate { append_instructions( ADC, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSBB register immediate { append_instructions( SBB, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSUB register immediate { append_instructions( SUB, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITXOR register immediate { append_instructions( XOR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITCMP register immediate { append_instructions( CMP, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITADD register memory { append_instructions( ADD, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITOR register memory { append_instructions( OR, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITADC register memory { append_instructions( ADC, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITSBB register memory { append_instructions( SBB, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITAND register memory { append_instructions( AND, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITSUB register memory { append_instructions( SUB, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITXOR register memory { append_instructions( XOR, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITCMP register memory { append_instructions( CMP, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITADD memory register { append_instructions( ADD, D32, MEM, $2, REG, $3.number ); }
|
|
| ITOR memory register { append_instructions( OR, D32, MEM, $2, REG, $3.number ); }
|
|
| ITADC memory register { append_instructions( ADC, D32, MEM, $2, REG, $3.number ); }
|
|
| ITSBB memory register { append_instructions( SBB, D32, MEM, $2, REG, $3.number ); }
|
|
| ITAND memory register { append_instructions( AND, D32, MEM, $2, REG, $3.number ); }
|
|
| ITSUB memory register { append_instructions( SUB, D32, MEM, $2, REG, $3.number ); }
|
|
| ITXOR memory register { append_instructions( XOR, D32, MEM, $2, REG, $3.number ); }
|
|
| ITCMP memory register { append_instructions( CMP, D32, MEM, $2, REG, $3.number ); }
|
|
| ITADD memory immediate { append_instructions( ADD, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITOR memory immediate { append_instructions( OR, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITADC memory immediate { append_instructions( ADC, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITSBB memory immediate { append_instructions( SBB, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITAND memory immediate { append_instructions( AND, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITSUB memory immediate { append_instructions( SUB, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITXOR memory immediate { append_instructions( XOR, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITCMP memory immediate { append_instructions( CMP, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITMOV register register { append_instructions( MOV, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITMOV register immediate { append_instructions( MOV, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITMOV register memory { append_instructions( MOV, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITMOV memory register { append_instructions( MOV, D32, MEM, $2, REG, $3.number ); }
|
|
| ITMOV memory immediate { append_instructions( MOV, $3.type, MEM, $2, $3.type, $3.value ); }
|
|
| ITROL register immediate { append_instructions( ROL, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITROR register immediate { append_instructions( ROR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITRCL register immediate { append_instructions( RCL, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITRCR register immediate { append_instructions( RCR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSAL register immediate { append_instructions( SAL, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSHR register immediate { append_instructions( SHR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSHL register immediate { append_instructions( SHL, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITROL memory immediate { append_instructions( ROL, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITROR memory immediate { append_instructions( ROR, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITRCL memory immediate { append_instructions( RCL, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITRCR memory immediate { append_instructions( RCR, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITSAL memory immediate { append_instructions( SAL, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITSHR memory immediate { append_instructions( SHR, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITSHL memory immediate { append_instructions( SHL, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITSAR memory immediate { append_instructions( SAR, D32, MEM, $2, $3.type, $3.value ); }
|
|
| ITLOOP relative { append_instructions( LOOP, D32, REL, $2 ); }
|
|
| ITLOOPE relative { append_instructions( LOOPE, D32, REL, $2 ); }
|
|
| ITLOOPNE relative { append_instructions( LOOPNE, D32, REL, $2 ); }
|
|
| ITPUSH register { append_instructions( PUSH, $2.size, REG, $2.number ); }
|
|
| ITPOP register { append_instructions( POP, $2.size, REG, $2.number ); }
|
|
|
|
// #placeholder<instruction_parser_rules> END
|
|
;
|
|
|
|
%%
|