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Merge branch 'master' of https://codeberg.org/eaxcc/eaxcc

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anon 2024-07-08 18:13:53 +02:00
commit 52a12f806a
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53
documentation/DEFINITION.md
View File

@ -30,6 +30,59 @@ options:
-o | --output <file>
-a | --architecture <architecture>
```
## Keywords -- XOLATILE EDIT PLEASE SOMEONE SANE REFACTOR LATER
- Not supporting legacy 8-bit register access ah, ch, dh, bh, all other accessing options are available.
- Please keep in mind that rCx and rDx go before rBx, order matters a lot, assembler trusts that user didn't make a mistake.
- Register accessing process (these are 64 keywords for registers):
```
| NUM | QWORD | DWORD | WORD | BYTE |
| NUM | 64 BIT | 32 BIT | 16 BIT | 8 BIT |
| 0 | rax | eax | ax | al |
| 1 | rcx | ecx | cx | cl |
| 2 | rdx | edx | dx | dl |
| 3 | rbx | ebx | bx | bl |
| 4 | rsp | esp | sp | spl |
| 5 | rbp | ebp | bp | bpl |
| 6 | rsi | esi | si | sil |
| 7 | rdi | edi | di | dil |
| 8 | r8 | r8d | r8w | r8b |
| 9 | r9 | r9d | r9w | r9b |
| A | r10 | r10d | r10w | r10b |
| B | r11 | r11d | r11w | r11b |
| C | r12 | r12d | r12w | r12b |
| D | r13 | r13d | r13w | r13b |
| E | r14 | r14d | r14w | r14b |
| F | r15 | r15d | r15w | r15b |
```
- For legacy and conventional reasons, we should however adopt stupid decisions made before we were born.
## Instructions
As for core instructions we must support, no matter what, here's the list:
```
mov <REG/MEM> <REG/MEM/IMM> -- immediate value can be up to 64 bits.
add or adc sbb and sub xor cmp <REG/MEM> <REG/MEM/IMM> -- immediate value can be up to 32 bits.
inc dec not neg mul imul div idiv <REG/MEM> -- no immediates allowed here.
jmp jCC cmovCC <> <> -- conditional instructions, important!
enter leave pop push -- stack focused instructions.
sysenter sysexit syscall sysret -- kernel/system focused instructions.
in out nop call bswap sal sar shr shl rol ror xchg loop -- ease-of-use focused instructions.
```
- ? ANON: Note that we can use 'loope' or 'loopne' instructions, since 'loop' is our keyword, but it can cause confusion...
- ? Keep in mind that for most of these instructions both destination and source can't be "memory addresses".
- Here is what's available to use, it's in the list below, there are 5 combinations, for 2 argument instructions.
```
ins REG REG -- mov, add, cmp, xor, and
ins REG MEM -- ^
ins REG IMM -- ^
ins MEM REG -- ^
ins MEM IMM -- ^
ins REG -- inc, dec, not, div, mul
ins MEM -- ^
ins -- syscall, pause, hlt, ret, leave
```
- ANON & EMIL: I leave other, HLA-related keywords to you guys, these above are important if we want powerful language.
- I'll implement a lot more instructions into assembler, but you can choose what to directly support by the HLA!
- For example, I'll have a procedure to generate machine code for 'loop' instruction, you can simply not use it when doing HLA->ASM.
## Types
```

22
documentation/heyo.asm
View File

@ -1,22 +0,0 @@
format ELF64 executable 3
segment readable executable
mov eax, 1
mov edi, 1
mov esi, heyo
mov edx, 12
syscall
mov eax, 60
mov edi, 0
syscall
segment readable writable
heyo: db "heyo world!", 10
; FASM
; 7F 45 4C 46 02 01 01 03 00 00 00 00 00 00 00 00 02 00 3E 00 01 00 00 00 B0 00 40 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 38 00 02 00 40 00 00 00 00 00 01 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 40 00 00 00 00 00 D2 00 00 00 00 00 00 00 D2 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 01 00 00 00 06 00 00 00 D2 00 00 00 00 00 00 00 D2 10 40 00 00 00 00 00 D2 10 40 00 00 00 00 00 0C 00 00 00 00 00 00 00 0C 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 B8 01 00 00 00 BF 01 00 00 00 BE D2 10 40 00 BA 0C 00 00 00 0F 05 B8 3C 00 00 00 BF 00 00 00 00 0F 05 68 65 79 6F 20 77 6F 72 6C 64 21 0A
; 7F 45 4C 46 02 01 01 03 00 00 00 00 00 00 00 00 02 00 3E 00 01 00 00 00 B0 00 40 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 38 00 02 00 40 00 00 00 00 00 01 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 40 00 00 00 00 00 C5 00 00 00 00 00 00 00 C5 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 01 00 00 00 06 00 00 00 C5 00 00 00 00 00 00 00 C5 10 40 00 00 00 00 00 C5 10 40 00 00 00 00 00 0C 00 00 00 00 00 00 00 0C 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 B8 01 00 00 00 BD 01 00 00 00 BC D2 10 40 00 BB 0C 00 00 00 0F 05 B8 3C 00 00 00 BD 00 00 00 00 0F 05 68 65 79 6F 20 77 6F 72 6C 64 21 0A
; EAXHLA

46
documentation/main_test.c
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@ -1,46 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include "../source/assembler.h"
#include "../source/assembler.c"
static unsigned int array [] = {
ADD, D64, REG, R1, REG, R9,
ADD, D64, REG, R1, MEM, 0,
ADD, D64, REG, R1, IMM, 0X11223344U,
ADD, D64, MEM, 0, REG, R9,
ADD, D64, MEM, 0, IMM, 0X11223344U,
OR, D32, REG, R1, REG, R9,
OR, D32, REG, R1, MEM, 0,
OR, D32, REG, R1, IMM, 0X11223344U,
OR, D32, MEM, 0, REG, R9,
OR, D32, MEM, 0, IMM, 0X11223344U,
ADC, D16, REG, R1, REG, R9,
ADC, D16, REG, R1, MEM, 0,
ADC, D16, REG, R1, IMM, 0X11223344U,
ADC, D16, MEM, 0, REG, R9,
ADC, D16, MEM, 0, IMM, 0X11223344U,
SBB, D8, REG, R1, REG, R9,
SBB, D8, REG, R1, MEM, 0,
SBB, D8, REG, R1, IMM, 0X11223344U,
SBB, D8, MEM, 0, REG, R9,
SBB, D8, MEM, 0, IMM, 0X11223344U
};
int main (void) {
unsigned int index;
token_array = malloc (144UL * sizeof (* token_array));
assemble ((unsigned int) (sizeof (array) / sizeof (array [0])), array);
printf ("> %u\n", token_count);
for (index = 0; index < token_count; ++index) {
printf ("%02X ", token_array [index]);
}
free (token_array);
return (0);
}

198
documentation/test.asm
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@ -1,198 +0,0 @@
format ELF64 executable 3
segment readable executable
entry $
nop
nop
nop
add rcx, r9
add rcx, [x8]
add rcx, 11223344h
add [x8], rcx
add qword[x8], 11223344h
or ecx, r9d
or ecx, [x4]
or ecx, 11223344h
or [x4], ecx
or dword[x4], 11223344h
adc cx, r9w
adc cx, [x2]
adc cx, 1122h
adc [x2], cx
adc word[x2], 1122h
sbb cl, r9b
sbb cl, [x1]
sbb cl, 11h
sbb [x1], cl
sbb byte[x1], 11h
;~add rcx r9 | ADD D64 REG R1 REG R9
;~4C 01 C9 | 4C 01 C9
;~add rcx [x8] | ADD D64 REG R1 MEM 0
;~48 03 0D E1 11 00 00 | 48 03 0D FF FF FF FF
;~add rcx 11223344h | ADD D64 REG R1 IMM 0X11223344U
;~48 81 C1 44 33 22 11 | 48 81 C2 44 33 22 11
;~^^ ^^
;~add [x8] rcx | ADD D64 MEM 0 REG R9
;~48 01 0D D3 11 00 00 | 4C 01 0D FF FF FF FF
;~^^ ^^
;~add [x8] 11223344h | ADD D64 MEM 0 IMM 0X11223344U
;~48 81 05 C8 11 00 00 44 33 22 11 | 48 81 05 FF FF FF FF 44 33 22 11
nop
nop
nop
xor rcx, r9
xor rcx, [x8]
xor rcx, 11223344h
xor [x8], rcx
xor qword[x8], 11223344h
xor ecx, r9d
xor ecx, [x4]
xor ecx, 11223344h
xor [x4], ecx
xor dword[x4], 11223344h
xor cx, r9w
xor cx, [x2]
xor cx, 1122h
xor [x2], cx
xor word[x2], 1122h
xor cl, r9b
xor cl, [x1]
xor cl, 11h
xor [x1], cl
xor byte[x1], 11h
nop
nop
nop
xor rcx, r9
xor rcx, [x8]
xor rcx, 11223344h
xor [x8], rcx
xor qword[x8], 11223344h
xor ecx, r9d
xor ecx, [x4]
xor ecx, 11223344h
xor [x4], ecx
xor dword[x4], 11223344h
xor cx, r9w
xor cx, [x2]
xor cx, 1122h
xor [x2], cx
xor word[x2], 1122h
xor cl, r9b
xor cl, [x1]
xor cl, 11h
xor [x1], cl
xor byte[x1], 11h
nop
nop
nop
inc rcx
inc qword[x8]
inc ecx
inc dword[x4]
inc cx
inc word[x2]
inc cl
inc byte[x1]
nop
nop
nop
div r9
div qword[x8]
div r9d
div dword[x4]
div r9w
div word[x2]
div r9b
div byte[x1]
nop
nop
nop
ret
leave
lock
hlt
nop
nop
nop
sysenter
sysexit
syscall
sysret
pause
cpuid
;~nop
;~nop
;~nop
;~jo fff
;~jno fff
;~jb fff
;~jae fff
;~je fff
;~jne fff
;~jbe fff
;~ja fff
;~js fff
;~jns fff
;~jpe fff
;~jpo fff
;~jl fff
;~jge fff
;~jle fff
;~jg fff
;~nop
;~nop
;~nop
;~cmovo rax, rcx
;~cmovno rax, rcx
;~cmovb rax, rcx
;~cmovae rax, rcx
;~cmove rax, rcx
;~cmovne rax, rcx
;~cmovbe rax, rcx
;~cmova rax, rcx
;~cmovs rax, rcx
;~cmovns rax, rcx
;~cmovpe rax, rcx
;~cmovpo rax, rcx
;~cmovl rax, rcx
;~cmovge rax, rcx
;~cmovle rax, rcx
;~cmovg rax, rcx
nop
nop
nop
;mov
;jmp
nop
nop
nop
segment readable writable
x1: db 011h
x2: dw 01122h
x4: dd 011223344h
x8: dq 01122334455667788h

8
source/assembler.c
View File

@ -132,10 +132,12 @@ static void build_regular (operation_index operation,
place (1, (byte) (0X08 * (operation - REGULAR_BEGIN)
+ (destination & 0X07) * ((to == REG) && (from == IMM))
+ 0X01 * ((to == MEM) && (from == IMM) && (size == D8)) //
- 0X01 * ((to == REG) && (from == IMM)) //
+ 0X01 * (size != D8)
+ 0X02 * ((from == MEM) && (to == REG))
+ 0X04 * ((from == IMM) && (to == MEM))
+ 0XC0 * ((from == IMM) && (to == REG))));
+ 0X02 * ((to == REG) && (from == MEM))
+ 0X04 * ((to == MEM) && (from == IMM))
+ 0XC0 * ((to == REG) && (from == IMM))));
build_register_direction ((to == REG) && (from == REG),
destination, source);

19
tool/heyo.asm Normal file
View File

@ -0,0 +1,19 @@
format ELF64 executable 3
segment readable executable
entry $
mov eax, 1
mov edi, 1
mov esi, heyo
mov edx, 12
syscall
mov eax, 60
mov edi, 0
syscall
segment readable writable
heyo: db "heyo world!", 10

21
tool/heyo_object.asm Normal file
View File

@ -0,0 +1,21 @@
format ELF64
public _start
section '.text' executable
_start:
mov eax, 1
mov edi, 1
mov esi, heyo
mov edx, 12
syscall
mov eax, 60
mov edi, 0
syscall
section '.data' writable
heyo: db "heyo world!", 10

27
tool/multiply.asm Normal file
View File

@ -0,0 +1,27 @@
format ELF64 executable 3
; fasm multiply.asm multiply
; chmod +x multiply
; ./multiply
; echo $?
; > 24
segment readable executable
entry $
mov eax, [a]
mov ecx, [b]
mul ecx
mov [c], eax
; exit (c);
mov eax, 60
mov edi, [c]
syscall
segment readable writable
a: dd 4
b: dd 6
c: dd 0; Expecting 24.

0
documentation/qfat.c → tool/qfat.c
View File

57
tool/system.asm Normal file
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@ -0,0 +1,57 @@
; General C to fasm reference, from xolatile, with hate...
; This is not intended to be assembled or ran in current state!
format ELF64 executable 3
; Executable and linkable file format, this can be done in HLA with:
; machine
; 0x7F "ELF" ... + some more "macro" magic ...
; end machine
segment readable executable
entry $; main: ...
; uint32_t a, b, c; c = a + b;
mov eax, [a]
add eax, [b]
mov [c], eax
; uint32_t a, b, c; c = a - b;
mov eax, [a]
sub eax, [b]
mov [c], eax
; uint32_t a, b, c; c = a * b;
mov eax, [a]
mul [b]
mov [c], eax
; uint32_t a, b, c; c = a / b;
mov eax, [a]
div [b]
mov [c], eax
; uint32_t a, b, c; c = a % b;
mov eax, [a]
div [b]
mov [c], edx
; exit (c);
mov eax, 60
mov edi, [c]
syscall
; This could be implemented also with 'end program'.
segment readable writable
a: db 11h ; uint8_t a = 0x11;
b: dw 1122h ; uint16_t b = 0x1122;
c: dd 11223344h ; uint32_t c = 0x11223344;
d: dq 1122334455667788h ; uint64_t d = 0x1122334455667788;
; I find null-terminated strings based and redpilled.
string_a: db "Heyo world!", 0 ; char string_a [] = "Heyo world!";
string_b: db "Heyo world!", 10, 0 ; char string_b [] = "Heyo world!\n";
string_c: db "Heyo world!", 0 ; char string_c [] = "Heyo world!";
string_c_length: dq $-string_c ; size_t string_c_length = sizeof (string_c);
; If you want to store the length of a string, it must be immediately after it.

223
tool/test.asm Normal file
View File

@ -0,0 +1,223 @@
format ELF64 executable 3
segment readable executable
entry $
nop
nop
nop
fff:
nop
add rcx, r9
nop
add rcx, [x8]
nop
add rcx, 11223344h
nop
add [x8], rcx
nop
add qword[x8], 11223344h
nop
or ecx, r9d
nop
or ecx, [x4]
nop
or ecx, 11223344h
nop
or [x4], ecx
nop
or dword[x4], 11223344h
nop
adc cx, r9w
nop
adc cx, [x2]
nop
adc cx, 1122h
nop
adc [x2], cx
nop
adc word[x2], 1122h
nop
sbb cl, r9b
nop
sbb cl, [x1]
nop
sbb cl, 11h
nop
sbb [x1], cl
nop
sbb byte[x1], 11h
nop
and rcx, r9
nop
and rcx, [x8]
nop
and rcx, 11223344h
nop
and [x8], rcx
nop
and qword[x8], 11223344h
nop
sub ecx, r9d
nop
sub ecx, [x4]
nop
sub ecx, 11223344h
nop
sub [x4], ecx
nop
sub dword[x4], 11223344h
nop
xor cx, r9w
nop
xor cx, [x2]
nop
xor cx, 1122h
nop
xor [x2], cx
nop
xor word[x2], 1122h
nop
cmp cl, r9b
nop
cmp cl, [x1]
nop
cmp cl, 11h
nop
cmp [x1], cl
nop
cmp byte[x1], 11h
nop
inc rcx
nop
inc qword[x8]
nop
inc ecx
nop
inc dword[x4]
nop
inc cx
nop
inc word[x2]
nop
inc cl
nop
inc byte[x1]
nop
div r9
nop
div qword[x8]
nop
div r9d
nop
div dword[x4]
nop
div r9w
nop
div word[x2]
nop
div r9b
nop
div byte[x1]
nop
ret
nop
leave
nop
lock
nop
hlt
nop
sysenter
nop
sysexit
nop
syscall
nop
sysret
nop
pause
nop
cpuid
nop
jo fff
nop
jno fff
nop
jb fff
nop
jae fff
nop
je fff
nop
jne fff
nop
jbe fff
nop
ja fff
nop
js fff
nop
jns fff
nop
jpe fff
nop
jpo fff
nop
jl fff
nop
jge fff
nop
jle fff
nop
jg fff
nop
cmovo rax, rcx
nop
cmovno rax, rcx
nop
cmovb rax, rcx
nop
cmovae rax, rcx
nop
cmove rax, rcx
nop
cmovne rax, rcx
nop
cmovbe rax, rcx
nop
cmova rax, rcx
nop
cmovs rax, rcx
nop
cmovns rax, rcx
nop
cmovpe rax, rcx
nop
cmovpo rax, rcx
nop
cmovl rax, rcx
nop
cmovge rax, rcx
nop
cmovle rax, rcx
nop
cmovg rax, rcx
;~;mov
;~;jmp
nop
nop
nop
nop
segment readable writable
x1: db 011h
x2: dw 01122h
x4: dd 011223344h
x8: dq 01122334455667788h

210
tool/test.c Normal file
View File

@ -0,0 +1,210 @@
#include <stdio.h>
#include <stdlib.h>
#include "../source/assembler.h"
#include "../source/assembler.c"
static unsigned int array [] = {
NOP, ADD, D64, REG, R1, REG, R9,
NOP, ADD, D64, REG, R1, MEM, 0,
NOP, ADD, D64, REG, R1, IMM, 0X11223344,
NOP, ADD, D64, MEM, 0, REG, R1,
NOP, ADD, D64, MEM, 0, IMM, 0X11223344,
NOP, OR, D32, REG, R1, REG, R9,
NOP, OR, D32, REG, R1, MEM, 0,
NOP, OR, D32, REG, R1, IMM, 0X11223344,
NOP, OR, D32, MEM, 0, REG, R1,
NOP, OR, D32, MEM, 0, IMM, 0X11223344,
NOP, ADC, D16, REG, R1, REG, R9,
NOP, ADC, D16, REG, R1, MEM, 0,
NOP, ADC, D16, REG, R1, IMM, 0X1122,
NOP, ADC, D16, MEM, 0, REG, R1,
NOP, ADC, D16, MEM, 0, IMM, 0X1122,
NOP, SBB, D8, REG, R1, REG, R9,
NOP, SBB, D8, REG, R1, MEM, 0,
NOP, SBB, D8, REG, R1, IMM, 0X11,
NOP, SBB, D8, MEM, 0, REG, R1,
NOP, SBB, D8, MEM, 0, IMM, 0X11,
NOP, AND, D64, REG, R1, REG, R9,
NOP, AND, D64, REG, R1, MEM, 0,
NOP, AND, D64, REG, R1, IMM, 0X11223344,
NOP, AND, D64, MEM, 0, REG, R1,
NOP, AND, D64, MEM, 0, IMM, 0X11223344,
NOP, SUB, D32, REG, R1, REG, R9,
NOP, SUB, D32, REG, R1, MEM, 0,
NOP, SUB, D32, REG, R1, IMM, 0X11223344,
NOP, SUB, D32, MEM, 0, REG, R1,
NOP, SUB, D32, MEM, 0, IMM, 0X11223344,
NOP, XOR, D16, REG, R1, REG, R9,
NOP, XOR, D16, REG, R1, MEM, 0,
NOP, XOR, D16, REG, R1, IMM, 0X1122,
NOP, XOR, D16, MEM, 0, REG, R1,
NOP, XOR, D16, MEM, 0, IMM, 0X1122,
NOP, CMP, D8, REG, R1, REG, R9,
NOP, CMP, D8, REG, R1, MEM, 0,
NOP, CMP, D8, REG, R1, IMM, 0X11,
NOP, CMP, D8, MEM, 0, REG, R1,
NOP, CMP, D8, MEM, 0, IMM, 0X11,
//~NOP, D32, INC, REG, R1,
//~NOP, D32, INC, MEM, 0,
//~NOP, D32, DEC, REG, R1,
//~NOP, D32, DEC, MEM, 0,
//~NOP, D32, NOT, REG, R1,
//~NOP, D32, NOT, MEM, 0,
//~NOP, D32, NEG, REG, R1,
//~NOP, D32, NEG, MEM, 0,
//~NOP, D32, UMUL, REG, R9,
//~NOP, D32, UMUL, MEM, 0,
//~NOP, D32, IMUL, REG, R9,
//~NOP, D32, IMUL, MEM, 0,
//~NOP, D32, UDIV, REG, R9,
//~NOP, D32, UDIV, MEM, 0,
//~NOP, D32, IDIV, REG, R9,
//~NOP, D32, IDIV, MEM, 0,
//~NOP, RETN,
//~NOP, RETF,
//~NOP, LEAVE,
//~NOP, LOCK,
//~NOP, HLT,
//~NOP, SYSENTER,
//~NOP, SYSEXIT,
//~NOP, SYSCALL,
//~NOP, SYSRET,
//~NOP, PAUSE,
//~NOP, CPUID,
//~NOP, JO, 0X77FFFFFF,
//~NOP, JNO, 0X77FFFFFF,
//~NOP, JB, 0X77FFFFFF,
//~NOP, JAE, 0X77FFFFFF,
//~NOP, JE, 0X77FFFFFF,
//~NOP, JNE, 0X77FFFFFF,
//~NOP, JBE, 0X77FFFFFF,
//~NOP, JA, 0X77FFFFFF,
//~NOP, JS, 0X77FFFFFF,
//~NOP, JNS, 0X77FFFFFF,
//~NOP, JPE, 0X77FFFFFF,
//~NOP, JPO, 0X77FFFFFF,
//~NOP, JL, 0X77FFFFFF,
//~NOP, JGE, 0X77FFFFFF,
//~NOP, JLE, 0X77FFFFFF,
//~NOP, JG, 0X77FFFFFF,
//~NOP, CMOVO, D64, REG, R0, REG, R1,
//~NOP, CMOVNO,D64, REG, R0, REG, R1,
//~NOP, CMOVB, D64, REG, R0, REG, R1,
//~NOP, CMOVAE, D64, REG, R0, REG, R1,
//~NOP, CMOVE, D64, REG, R0, REG, R1,
//~NOP, CMOVNE, D64, REG, R0, REG, R1,
//~NOP, CMOVBE, D32, REG, R0, REG, R1,
//~NOP, CMOVA, D32, REG, R0, REG, R1,
//~NOP, CMOVS, D32, REG, R0, REG, R1,
//~NOP, CMOVNS, D32, REG, R0, REG, R1,
//~NOP, CMOVPE, D32, REG, R0, REG, R1,
//~NOP, CMOVPO, D32, REG, R0, REG, R1,
//~NOP, CMOVL, D32, REG, R0, REG, R1,
//~NOP, CMOVGE, D32, REG, R0, REG, R1,
//~NOP, CMOVLE, D16, REG, R0, REG, R1,
//~NOP, CMOVG, D16, REG, R0, REG, R1
};
int main (void) {
unsigned int index;
token_array = malloc (1440UL * sizeof (* token_array));
assemble ((unsigned int) (sizeof (array) / sizeof (array [0])), array);
printf ("> %u\n", token_count);
for (index = 0; index < token_count; ++index) {
printf ("%02X ", token_array [index]);
}
free (token_array);
return (0);
}
/*
XOLATILE: FLAT:
4C 01 C9 4C 01 C9
48 03 0D FF FF FF FF 48 03 0D 52 12 00 00
48 81 C2 44 33 22 11 48 81 C1 44 33 22 11 add rcx 0X11223344 -1
48 01 0D FF FF FF FF 48 01 0D 42 12 00 00
48 81 05 FF FF FF FF 44 33 22 11 48 81 05 36 12 00 00 44 33 22 11
44 09 C9 44 09 C9
0B 0D FF FF FF FF 0B 0D 27 12 00 00
81 CA 44 33 22 11 81 C9 44 33 22 11 or ecx 0X11223344 -2
09 0D FF FF FF FF 09 0D 19 12 00 00
81 0D FF FF FF FF 44 33 22 11 81 0D 0E 12 00 00 44 33 22 11
66 44 11 C9 66 44 11 C9
66 13 0D FF FF FF FF 66 13 0D FF 11 00 00
66 81 D2 22 11 66 81 D1 22 11 adc cx 0X1122 -1
66 11 0D FF FF FF FF 66 11 0D F1 11 00 00
66 81 15 FF FF FF FF 22 11 66 81 15 E7 11 00 00 22 11
44 18 C9 44 18 C9
1A 0D FF FF FF FF 1A 0D DB 11 00 00
80 D9 11 80 D9 11
18 0D FF FF FF FF 18 0D D0 11 00 00
80 1C FF FF FF FF 11 80 1D C8 11 00 00 11 sbb [1] 0X11 +1
4C 21 C9 4C 21 C9
48 23 0D FF FF FF FF 48 23 0D C3 11 00 00
48 81 E2 44 33 22 11 48 81 E1 44 33 22 11 and rcx 0X11223344 -1
48 21 0D FF FF FF FF 48 21 0D B3 11 00 00
48 81 25 FF FF FF FF 44 33 22 11 48 81 25 A7 11 00 00 44 33 22 11
44 29 C9 44 29 C9
2B 0D FF FF FF FF 2B 0D 98 11 00 00
81 EA 44 33 22 11 81 E9 44 33 22 11 sub ecx 0X11223344 -2
29 0D FF FF FF FF 29 0D 8A 11 00 00
81 2D FF FF FF FF 44 33 22 11 81 2D 7F 11 00 00 44 33 22 11
66 44 31 C9 66 44 31 C9
66 33 0D FF FF FF FF 66 33 0D 70 11 00 00
66 81 F2 22 11 66 81 F1 22 11 xor cx 0X1122 -1
66 31 0D FF FF FF FF 66 31 0D 62 11 00 00
66 81 35 FF FF FF FF 22 11 66 81 35 58 11 00 00 22 11
44 38 C9 44 38 C9
3A 0D FF FF FF FF 3A 0D 4C 11 00 00
80 F9 11 80 F9 11
38 0D FF FF FF FF 38 0D 41 11 00 00
80 3C FF FF FF FF 11 ****************************************
FASM:
90 4C 01 C9
90 48 03 0D 52 12 00 00
90 48 81 C1 44 33 22 11
90 48 01 0D 42 12 00 00
90 48 81 05 36 12 00 00 44 33 22 11
90 44 09 C9
90 0B 0D 27 12 00 00
90 81 C9 44 33 22 11
90 09 0D 19 12 00 00
90 81 0D 0E 12 00 00 44 33 22 11
90 66 44 11 C9
90 66 13 0D FF 11 00 00
90 66 81 D1 22 11
90 66 11 0D F1 11 00 00
90 66 81 15 E7 11 00 00 22 11
90 44 18 C9
90 1A 0D DB 11 00 00
90 80 D9 11
90 18 0D D0 11 00 00
90 80 1D C8 11 00 00 11
90 4C 21 C9
90 48 23 0D C3 11 00 00
90 48 81 E1 44 33 22 11
90 48 21 0D B3 11 00 00
90 48 81 25 A7 11 00 00 44 33 22 11
90 44 29 C9
90 2B 0D 98 11 00 00
90 81 E9 44 33 22 11
90 29 0D 8A 11 00 00
90 81 2D 7F 11 00 00 44 33 22 11
90 66 44 31 C9
90 66 33 0D 70 11 00 00
90 66 81 F1 22 11
90 66 31 0D 62 11 00 00
90 66 81 35 58 11 00 00 22 11
90 44 38 C9
90 3A 0D 4C 11 00 00
90 80 F9 11
90 38 0D 41 11 00 00
*/

0
documentation/xfat.c → tool/xfat.c
View File