less terrible instruction generation
This commit is contained in:
anon
4
Makefile
4
Makefile
@ -79,14 +79,14 @@ test: ${OUT}
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clean:
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-rm ${OUT} ${OBJECT} ${GENOBJECT} ${GENSOURCE}
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${OBJECT.d}/%.pp: debug/%.tcl
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${OBJECT.d}/%.pp: debug/%.tcl debug/instructions.tcl
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tclsh $< > $@
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plug: ${OBJECT.d}/token_list.pp ${OBJECT.d}/scanner_instructions.pp ${OBJECT.d}/parser_rules.pp
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plug -u -d token_list '' -d scanner_instructions '' -d parser_rules '' source/eaxhla.l source/eaxhla.y
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plug -g -e token_list ${OBJECT.d}/token_list.pp source/eaxhla.y
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plug -g -e scanner_instructions ${OBJECT.d}/scanner_instructions.pp source/eaxhla.l
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plug -g -e parser_rules ${OBJECT.d}/parser_rules.pp source/eaxhla.l
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plug -g -e parser_rules ${OBJECT.d}/parser_rules.pp source/eaxhla.y
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.PHONY: test clean bootstrap
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@ -1,6 +1,5 @@
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set instructions {
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{syscall}
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{nop}
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{sysret}
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{sysexit}
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{sysenter}
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@ -10,6 +9,30 @@ set instructions {
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{pause}
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{hlt}
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{lock}
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{inc register}
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{dec register}
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{not register}
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{neg register}
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{mul register}
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{imul register}
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{div register}
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{idiv register}
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{inc memory}
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{dec memory}
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{not memory}
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{neg memory}
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{mul memory}
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{imul memory}
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{div memory}
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{idiv memory}
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{add register register}
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{or register register}
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{adc register register}
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{sbb register register}
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{and register register}
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{sub register register}
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{xor register register}
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{cmp register register}
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}
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# {mov register immediate}
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@ -1,62 +1,71 @@
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source debug/instructions.tcl
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proc make_parser_rules {is} {
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proc type_name_to_type_enum {n} {
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switch $n {
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"register" {
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return "REG"
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proc init_iarg {a n} {
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set r [dict create]
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switch $a {
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"register" {
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dict set r enum "REG"
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dict set r value "\$$n.number"
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dict set r size "\$$n.size"
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}
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"immediate" {
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return "IMM"
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dict set r enum "IMM"
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dict set r value "(int)$e"
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dict set r size "32"
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}
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"memory" {
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return "MEM"
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}
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default {
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malformed_instruction $n
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}
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}
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}
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proc type_name_to_type_value {n e} {
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switch $n {
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"register" {
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return "$e.number"
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}
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"immediate" {
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return "(int)$e"
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}
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"memory" {
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return "???"
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}
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default {
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malformed_instruction $n
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"memory" {
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dict set r enum "MEM"
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dict set r value "0 /* ??? */"
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dict set r size "0 /* ??? */"
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}
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default { malformed_instruction $n }
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}
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return $r
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}
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proc make_parser_rule {i} {
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if {[llength $i] == 1} {
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set rule [format " | I%s { append_instruction_t1(%s); }" \
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set rule [format " | IT%s { append_instruction_t1(%s); }" \
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[string toupper [lindex $i 0]] \
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[string toupper [lindex $i 0]] \
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[string toupper [lindex $i 0]]
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]
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} elseif {[llength $i] == 3} {
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set rule [format " | I%s %s %s \{ append_instruction_t4(\
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%s,\
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\$2.size,\
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} elseif {[llength $i] == 2} {
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set arg [init_iarg [lindex $i 1] 2]
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set rule [format " | IT%s %s \{ append_instruction_t4(\
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%s,\
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%s,\
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%s,\
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%s\
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);" \
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); \}" \
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[string toupper [lindex $i 0]] \
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[lindex $i 1] \
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\
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[string toupper [lindex $i 0]] \
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[dict get $arg size] \
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[dict get $arg enum] \
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[dict get $arg value] \
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]
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} elseif {[llength $i] == 3} {
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set arg1 [init_iarg [lindex $i 1] 2]
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set arg2 [init_iarg [lindex $i 2] 3]
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set rule [format " | IT%s %s %s \{ append_instruction_t6(\
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%s,\
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%s,\
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%s,\
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%s,\
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%s,\
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%s\
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); \}" \
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[string toupper [lindex $i 0]] \
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[lindex $i 1] \
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[lindex $i 2] \
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\
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[string toupper [lindex $i 0]] \
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[type_name_to_type_enum [lindex $i 1]] \
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[type_name_to_type_value [lindex $i 1] "\$2"] \
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[type_name_to_type_enum [lindex $i 2]] \
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[type_name_to_type_value [lindex $i 2] "\$3"] \
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[dict get $arg1 size] \
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[dict get $arg1 enum] \
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[dict get $arg1 value] \
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[dict get $arg2 enum] \
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[dict get $arg2 value] \
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]
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} else {
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malformed_instruction $i
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@ -2,7 +2,7 @@ source debug/instructions.tcl
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proc make_scanner_instructions {is} {
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proc make_scanner_instruction {i} {
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puts [format "%s { return I%s; }" \
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puts [format "%s { return IT%s; }" \
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[lindex $i 0] \
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[string toupper [lindex $i 0]]
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]
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@ -12,4 +12,6 @@ proc make_scanner_instructions {is} {
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}
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}
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puts " */"
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make_scanner_instructions $instructions
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@ -1,9 +1,16 @@
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source debug/instructions.tcl
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proc make_token_list {is} {
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proc uniq_instl {is} {
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set r []
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foreach i $is {
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lappend r [lindex $i 0]
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}
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return [lsort -unique $r]
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}
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puts -nonewline "%token"
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foreach i $is {
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puts -nonewline [format " I%s" [string toupper [lindex $i 0]]]
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foreach i [uniq_instl $is] {
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puts -nonewline [format " IT%s" [string toupper [lindex $i 0]]]
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}
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}
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@ -103,8 +103,8 @@ u64 { return U64; }
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\" { BEGIN IN_STRING; }
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\!\= { return NEQ; }
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\! { return TNOT; }
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\!\= { return ITNEQ; }
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\! { return ITNOT; }
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\/\/ { BEGIN IN_COMMENT; }
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\/\* { BEGIN IN_MULTILINE_COMMENT; }
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@ -116,15 +116,45 @@ u64 { return U64; }
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fastcall { return FASTCALL; }
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/* --- Instrunctions begin here --- */
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/*
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xor{wsnl}+ { return TXOR; }
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inc{wsnl}+ { return TINC; }
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nop { return INOP; }
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/* #placeholder<scanner_instructions> BEGIN
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*/
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add { return IADD; }
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syscall { return ISYSCALL; }
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mov { return IMOV; }
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xor { return IXOR; }
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/* #placeholder<scanner_instructions> COLLAPSED
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syscall { return ITSYSCALL; }
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sysret { return ITSYSRET; }
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sysexit { return ITSYSEXIT; }
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sysenter { return ITSYSENTER; }
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leave { return ITLEAVE; }
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retf { return ITRETF; }
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retn { return ITRETN; }
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pause { return ITPAUSE; }
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hlt { return ITHLT; }
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lock { return ITLOCK; }
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inc { return ITINC; }
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dec { return ITDEC; }
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not { return ITNOT; }
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neg { return ITNEG; }
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mul { return ITMUL; }
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imul { return ITIMUL; }
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div { return ITDIV; }
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idiv { return ITIDIV; }
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inc { return ITINC; }
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dec { return ITDEC; }
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not { return ITNOT; }
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neg { return ITNEG; }
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mul { return ITMUL; }
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imul { return ITIMUL; }
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div { return ITDIV; }
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idiv { return ITIDIV; }
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add { return ITADD; }
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or { return ITOR; }
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adc { return ITADC; }
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sbb { return ITSBB; }
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and { return ITAND; }
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sub { return ITSUB; }
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xor { return ITXOR; }
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cmp { return ITCMP; }
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/* #placeholder<scanner_instructions> END
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*/
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/* --- Instrunctions end here --- */
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@ -52,9 +52,9 @@
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%token UNIX WIN64
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// Logic
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%token NEQ TNOT
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%token ITNEQ
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/*
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%token TOR TXOR // these are (in)conveniently instructions too
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%token ITOR ITXOR ITAND ITNOT // these are (in)conveniently instructions too
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*/
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// Type info
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@ -79,13 +79,10 @@
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%token RG8D RG9D RG10D RG11D RG12D RG13D RG14D RG15D
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// Instructions
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%token TADD TOR TADC TBB TXOR TAND TSUB TCMP TSYSCALL TINC
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%token INOP // better temp prefix?
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%token IADD
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%token ISYSCALL
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%token IMOV
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%token IXOR
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// #placeholder<token_list> COLLAPSED
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%token INOP
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// #placeholder<token_list> BEGIN
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%token ITADC ITADD ITAND ITCMP ITDEC ITDIV ITHLT ITIDIV ITIMUL ITINC ITLEAVE ITLOCK ITMUL ITNEG ITNOT ITOR ITPAUSE ITRETF ITRETN ITSBB ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITXOR
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// #placeholder<token_list> END
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// Instruction-likes
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%token FASTCALL
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@ -208,28 +205,6 @@ code: %empty
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| instruction code
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;
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instruction: INOP { ; }
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/*
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| TXOR register register code { /* assemble_xor(size_64b, type_register_register, $2, $3); * / }
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| TXOR register immediate code { /* assemble_xor(size_64b, type_register_register, $2, $3); * / }
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| TXOR IDENTIFIER register code { /* assemble_xor(size_64b, type_register_register, $2, $3); * / free($2); }
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| TINC register code
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| TINC IDENTIFIER code { free($2); }
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*/
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| IADD register register
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| IADD register immediate
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| IADD register memory
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| ISYSCALL { append_instruction_t1 (SYSCALL); }
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| IMOV register register
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| IMOV memory register
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| IMOV register memory
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| IMOV register immediate { append_instruction_t6 (MOV, $2.size, REG, $2.number, IMM, (int) $3); }
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| IMOV memory immediate
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| IXOR register register
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| IXOR register memory
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// #placeholder<parser_rules> COLLAPSED
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;
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repeat: REPEAT code END_REPEAT
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;
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@ -237,13 +212,13 @@ if: IF logic THEN code END_IF
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| IF logic THEN code ELSE code END_IF
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;
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logic: logical_operand TAND logical_operand
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| logical_operand TOR logical_operand
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| logical_operand TXOR logical_operand
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| logical_operand '=' logical_operand
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| logical_operand NEQ logical_operand
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logic: logical_operand ITAND logical_operand
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| logical_operand ITOR logical_operand
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| logical_operand ITXOR logical_operand
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| logical_operand '=' logical_operand
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| logical_operand ITNEQ logical_operand
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| sublogic
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| TNOT logic
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| ITNOT logic
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;
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logical_operand: sublogic
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@ -345,4 +320,49 @@ artimetric_operand: LITERAL
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exit: EXIT value
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;
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instruction: INOP { append_instruction_t1(NOP); }
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/*
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| ISYSCALL { append_instruction_t1 (SYSCALL); }
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| IMOV register immediate { append_instruction_t6 (MOV, $2.size, REG, $2.number, IMM, (int) $3); }
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*/
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// #placeholder<parser_rules> BEGIN
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| ITSYSCALL { append_instruction_t1(SYSCALL); }
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| ITSYSRET { append_instruction_t1(SYSRET); }
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| ITSYSEXIT { append_instruction_t1(SYSEXIT); }
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| ITSYSENTER { append_instruction_t1(SYSENTER); }
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| ITLEAVE { append_instruction_t1(LEAVE); }
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| ITRETF { append_instruction_t1(RETF); }
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| ITRETN { append_instruction_t1(RETN); }
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| ITPAUSE { append_instruction_t1(PAUSE); }
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| ITHLT { append_instruction_t1(HLT); }
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| ITLOCK { append_instruction_t1(LOCK); }
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| ITINC register { append_instruction_t4( INC, $2.size, REG, $2.number ); }
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| ITDEC register { append_instruction_t4( DEC, $2.size, REG, $2.number ); }
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| ITNOT register { append_instruction_t4( NOT, $2.size, REG, $2.number ); }
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| ITNEG register { append_instruction_t4( NEG, $2.size, REG, $2.number ); }
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| ITMUL register { append_instruction_t4( MUL, $2.size, REG, $2.number ); }
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| ITIMUL register { append_instruction_t4( IMUL, $2.size, REG, $2.number ); }
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| ITDIV register { append_instruction_t4( DIV, $2.size, REG, $2.number ); }
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| ITIDIV register { append_instruction_t4( IDIV, $2.size, REG, $2.number ); }
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| ITINC memory { append_instruction_t4( INC, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITDEC memory { append_instruction_t4( DEC, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITNOT memory { append_instruction_t4( NOT, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITNEG memory { append_instruction_t4( NEG, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITMUL memory { append_instruction_t4( MUL, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITIMUL memory { append_instruction_t4( IMUL, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITDIV memory { append_instruction_t4( DIV, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITIDIV memory { append_instruction_t4( IDIV, 0 /* ??? */, MEM, 0 /* ??? */ ); }
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| ITADD register register { append_instruction_t6( ADD, $2.size, REG, $2.number, REG, $3.number ); }
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| ITOR register register { append_instruction_t6( OR, $2.size, REG, $2.number, REG, $3.number ); }
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| ITADC register register { append_instruction_t6( ADC, $2.size, REG, $2.number, REG, $3.number ); }
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| ITSBB register register { append_instruction_t6( SBB, $2.size, REG, $2.number, REG, $3.number ); }
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| ITAND register register { append_instruction_t6( AND, $2.size, REG, $2.number, REG, $3.number ); }
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| ITSUB register register { append_instruction_t6( SUB, $2.size, REG, $2.number, REG, $3.number ); }
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| ITXOR register register { append_instruction_t6( XOR, $2.size, REG, $2.number, REG, $3.number ); }
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| ITCMP register register { append_instruction_t6( CMP, $2.size, REG, $2.number, REG, $3.number ); }
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// #placeholder<parser_rules> END
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;
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%%
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Reference in New Issue
Block a user