major stress test compiles

This commit is contained in:
anon
2024-07-23 23:54:05 +02:00
parent c17348f18d
commit daeaace9f8
6 changed files with 10 additions and 7 deletions

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@ -21,10 +21,10 @@ syn keyword eaxType u8 u16 u32 u64 s8 s16 s32 s64
syn keyword eaxInstruction inc xor mov syn keyword eaxInstruction inc xor mov
syn keyword eaxInstructionLike fastcall exit syn keyword eaxInstructionLike fastcall exit
syn keyword eaxRegister syn keyword eaxRegister
\ rax rcx rdx rbx rsp rbp rsi rdi rg8 rg9 rg10 rg11 rg12 rg13 rg14 rg15 \ rax rcx rdx rbx rsp rbp rsi rdi r8 r9 r10 r11 r12 r13 r14 r15
\ eax ecx edx ebx esp ebp esi edi rg8d rg9d rg10d rg11d rg12d rg13d rg14d rg15d \ eax ecx edx ebx esp ebp esi edi r8d r9d r10d r11d r12d r13d r14d r15d
\ ax cx dx bx sp bp si di r8w r9w r10w r11w r12w r13w r14w r15w \ ax cx dx bx sp bp si di r8w r9w r10w r11w r12w r13w r14w r15w
\ al cl dl bl spl bpl sil dil r8b r9b r10b r11b r12b r13b r14b r15b \ al cl dl bl spl bpl sil dil r8b r9b r10b r11b r12b r13b r14b r15b
syn match eaxInt "\-\?\d\+" syn match eaxInt "\-\?\d\+"
syn match eaxHex "0x[0-9a-fA-F]\+" syn match eaxHex "0x[0-9a-fA-F]\+"
syn match eaxBin "0b\[01\]\+" syn match eaxBin "0b\[01\]\+"

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@ -211,13 +211,14 @@ library { BEGIN INITIAL; return END_LIBRARY; }
*/ */
/* XXX: THIS CODE IS TOTAL DEATH /* XXX: THIS CODE IS TOTAL DEATH
*/ */
. { char_literal_buffer = yytext[0]; }
\n { char_literal_buffer = '\n'; } \n { char_literal_buffer = '\n'; }
\' { \' {
BEGIN INITIAL;
yylval.intval = char_literal_buffer; yylval.intval = char_literal_buffer;
char_literal_buffer = 0; char_literal_buffer = 0;
return LITERAL; return LITERAL;
} }
. { char_literal_buffer = yytext[0]; }
\n { issue_error("unterminated character literal sequence"); yyterminate(); } \n { issue_error("unterminated character literal sequence"); yyterminate(); }
} }

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@ -458,6 +458,7 @@ instruction: INOP { append_instructions(NOP); }
| ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); } | ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); }
| ITSBB register register { append_instructions( SBB, $2.size, REG, $2.number, REG, $3.number ); } | ITSBB register register { append_instructions( SBB, $2.size, REG, $2.number, REG, $3.number ); }
| ITAND register register { append_instructions( AND, $2.size, REG, $2.number, REG, $3.number ); } | ITAND register register { append_instructions( AND, $2.size, REG, $2.number, REG, $3.number ); }
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
| ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); } | ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); }
| ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); } | ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); }
| ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); } | ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); }

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@ -20,7 +20,7 @@ end procedure
unix program main unix program main
begin begin
nop mov rg10d 0x11223344 nop mov r10d 0x11223344
nop fastcall heyo nop fastcall heyo
nop fastcall cyaa nop fastcall cyaa
nop fastcall heyo nop fastcall heyo

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@ -87,7 +87,7 @@ begin
mov r13d digits mov r13d digits
sar r15d 4 sar r15d 4
add r13d r15d add r13d r15d
call write_character fastcall write_character
mov r12d 1 mov r12d 1
mov r13d digits mov r13d digits

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@ -34,6 +34,7 @@ set instructions {
{adc register register} {adc register register}
{sbb register register} {sbb register register}
{and register register} {and register register}
{and register immediate}
{sub register register} {sub register register}
{xor register register} {xor register register}
{cmp register register} {cmp register register}