Added instructions into generator...
This commit is contained in:
xolatile
parent
fae1aedeb5
commit
facd80e228
@ -2,62 +2,62 @@
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#define ASSEMBLER_H
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enum {
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D8, // 8-bit
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D16, // 16-bit
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D32, // 32-bit
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D64 // 64-bit
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D8,
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D16,
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D32,
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D64
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};
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enum {
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REL, // Relative
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REG, // Register
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MEM, // Memory
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IMM // Immediate
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REL,
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REG,
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MEM,
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IMM
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};
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enum {
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ASMDIRMEM, // Insert memory address directive.
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ASMDIRREL, // Insert relative address directive.
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ASMDIRIMM, // Insert immediate literal directive.
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ASMDIRREP, // Repeat directive.
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ADD, // Add registers or memory addresses.
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OR, // Bit-or registers or memory addresses.
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ADC, // Add-carry registers or memory addresses.
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SBB, // Subtract-borrow registers or memory addresses.
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AND, // Bit-and registers or memory addresses.
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SUB, // Subtract registers or memory addresses.
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XOR, // Bit-xor registers or memory addresses.
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CMP, // Compare registers or memory addresses.
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INC, // Increment register or memory address.
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DEC, // Decrement register or memory address.
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NOT, // Bit-not register or memory address.
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NEG, // Negate register or memory address.
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MUL, // Multiply register or memory address.
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IMUL, // Sign-multiply register or memory address.
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DIV, // Divide register or memory address.
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IDIV, // Sign-divide register or memory address.
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NOP, // No operation, skip a cycle.
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RETN, // Near return to calling procedure.
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RETF, // Far return to calling procedure.
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LEAVE, // Release the stack frame set up by enter.
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LOCK, // Assert CPU lock signal during execution.
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HLT, // Stop execution and set CPU to halt state.
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POPF, // Pop stack into flags register (16/64 bit).
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PUSHF, // Push flags register onto stack (16/64 bit).
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WAIT, // Check for and handle pending float exceptions.
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CLC, // Clear carry flag.
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CLD, // Clear direction flag.
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CLI, // Clear interrupt flag.
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STC, // Set carry flag.
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STD, // Set direction flag.
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STI, // Set interrupt flag.
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CMC, // Complement carry flag.
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INSB, // Input 1 byte from IO port at DX to ES:(E)DI or RDI.
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INSD, // Input 4 bytes from IO port at DX to ES:(E)DI or RDI.
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OUTSB, // Output 1 byte from DS:(E)SI or RSI to IO port at DX.
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OUTSD, // Output 4 bytes from DS:(E)SI or RSI to IO port at DX.
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CDQ, // Sign-extend EAX into EDX:EAX.
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CWDE, // Sign-extend AX into EAX.
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ASMDIRMEM,
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ASMDIRREL,
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ASMDIRIMM,
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ASMDIRREP,
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ADD,
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OR,
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ADC,
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SBB,
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AND,
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SUB,
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XOR,
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CMP,
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INC,
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DEC,
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NOT,
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NEG,
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MUL,
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IMUL,
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DIV,
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IDIV,
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NOP,
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RETN,
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RETF,
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LEAVE,
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LOCK,
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HLT,
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POPF,
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PUSHF,
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WAIT,
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CLC,
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CLD,
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CLI,
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STC,
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STD,
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STI,
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CMC,
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INSB,
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INSD,
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OUTSB,
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OUTSD,
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CDQ,
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CWDE,
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INAL,
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INEAX,
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INT3,
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@ -70,42 +70,42 @@ enum {
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SCASD,
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STOSB,
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STOSD,
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SYSENTER, // Execute fast call to ring 0 system procedure.
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SYSEXIT, // Execute fast return to ring 3 userland procedure.
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SYSCALL, // Execute OS system call handler at kernel.
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SYSRET, // Execute return from previous system call.
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PAUSE, // Hint CPU for usage of spin-wait loop.
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CPUID, // Request CPU identification and information.
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EMMS, // Empty MMX technology state (x87 FPU).
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RSM, // Resume execution from system management mode.
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FNOP, // No operation, skip cycle (x87 FPU).
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FCHS, // Complement sign of st0.
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FABS, // Replace st0 with its absolute value.
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FTST, // Compare st0 with 0.0 literal.
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FXAM, // Classify value or literal in st0.
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FLD1, // Push 1.0 literal to FPU stack.
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FLDL2T, // Push log2 (10) literal to FPU stack.
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FLDL2E, // Push log2 (e) literal to FPU stack.
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FLDPI, // Push pi literal to FPU stack.
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FLDLG2, // Push log10 (2) literal to FPU stack.
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FLDLN2, // Push loge (2) literal to FPU stack.
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FLDZ, // Push 0.0 literal to FPU stack.
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F2XM1, // Replace st0 with 2.0**st0 - 1.0.
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FYL2X, // Multiply st1 with log2 (st0), pop FPU stack.
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FPTAN, // Compute tan (st0), push 1.0 to FPU stack.
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FPATAN, // Compute arctan (st1 / st0), pop FPU stack.
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FXTRACT, // Separate st0 into FP elements, push FPU stack.
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FPREM1, // Replace st0 with st0 % st1, round up.
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FDECSTP, // Decrement FPU stack pointer.
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FINCSTP, // Increment FPU stack pointer.
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FPREM, // Replace st0 with st0 % st1.
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FYL2XP1, // Multiply st1 with log2 (st0) + 1.0, pop FPU stack.
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FSQRT, // Compute square root of st0.
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FSINCOS, // Compure sin (st0), push cos (st0) to FPU stack.
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FRNDINT, // Round st0 to integer value.
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FSCALE, // Scale st0 by st1.
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FSIN, // Compute sin (st0).
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FCOS, // Compure cos (st0).
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SYSENTER,
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SYSEXIT,
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SYSCALL,
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SYSRET,
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PAUSE,
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CPUID,
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EMMS,
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RSM,
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FNOP,
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FCHS,
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FABS,
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FTST,
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FXAM,
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FLD1,
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FLDL2T,
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FLDL2E,
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FLDPI,
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FLDLG2,
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FLDLN2,
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FLDZ,
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F2XM1,
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FYL2X,
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FPTAN,
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FPATAN,
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FXTRACT,
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FPREM1,
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FDECSTP,
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FINCSTP,
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FPREM,
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FYL2XP1,
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FSQRT,
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FSINCOS,
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FRNDINT,
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FSCALE,
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FSIN,
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FCOS,
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INSW,
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OUTSW,
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CWD,
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@ -130,98 +130,98 @@ enum {
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STOSQ,
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WRMSR,
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XLATB,
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ENTER, // Create a stack frame for procedure call.
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CALL, // Call near, relative or absolute procedure.
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IN, // Input byte from 8-bit IO port to r0.
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OUT, // Output byte from r0 to 8-bit IO port.
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JMP, // Jump near, far, relative or absolute offset.
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JO, // Conditional jump on overflow flag set.
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JNO, // Conditional jump on not overflow flag set.
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JB, // Conditional jump on below flag set.
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JAE, // Conditional jump on above or equal flag set.
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JE, // Conditional jump on equal flag set.
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JNE, // Conditional jump on not equal flag set.
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JBE, // Conditional jump on below or equal flag set.
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JA, // Conditional jump on above flag set.
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JS, // Conditional jump on negative flag set.
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JNS, // Conditional jump on positive flag set.
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JPE, // Conditional jump on parity even flag set.
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JPO, // Conditional jump on parity odd flag set.
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JL, // Conditional jump on less flag set.
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JGE, // Conditional jump on greater or equal flag set.
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JLE, // Conditional jump on less or equal flag set.
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JG, // Conditional jump on greater flag set.
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MOV, // Move registers or memory addresses.
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CMOVO, // Conditional move on overflow flag set.
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CMOVNO, // Conditional move on not overflow flag set.
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CMOVB, // Conditional move on below flag set.
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CMOVAE, // Conditional move on above or equal flag set.
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CMOVE, // Conditional move on equal flag set.
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CMOVNE, // Conditional move on not equal flag set.
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CMOVBE, // Conditional move on below or equal flag set.
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CMOVA, // Conditional move on above flag set.
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CMOVS, // Conditional move on negative flag set.
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CMOVNS, // Conditional move on positive flag set.
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CMOVPE, // Conditional move on parity even flag set.
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CMOVPO, // Conditional move on parity odd flag set.
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CMOVL, // Conditional move on less flag set.
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CMOVGE, // Conditional move on greater or equal flag set.
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CMOVLE, // Conditional move on less or equal flag set.
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CMOVG, // Conditional move on greater flag set.
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PUSH, // Push a value to stack.
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POP, // Pop a value from stack.
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BSWAP, // Swap bytes according to little-endian rules.
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TEST, // And registers or memory addresses, set flags.
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RCL, // Rotate-carry bits left, repeat r1 times.
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RCR, // Rotate-carry bits right, repeat r1 times.
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ROL, // Rotate bits left, repeat r1 times.
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ROR, // Rotate bits right, repeat r1 times.
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SHL, // Shift bits left, repeat r1 times.
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SHR, // Sign-shift bits right, repeat r1 times.
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SAL, // Shift bits left, repeat r1 times.
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SAR, // Shift bits right, repeat r1 times.
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REP, // Repeat string instruction.
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REPE, // Repeat string instruction while equal.
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REPNE, // Repeat string instruction while not equal.
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REPZ, // Repeat string instruction while zero.
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REPNZ, // Repeat string instruction while not zero.
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LOOP, // Decrement r1, jump near if not zero.
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LOOPE, // Decrement r1, jump near if not zero and zflag.
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LOOPNE, // Decrement r1, jump near if not zero and not zflag.
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MOVBE, // Swap bytes and move register or memory address.
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XADD, // Exchange and add register and memory address.
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XCHG, // Exchange registers or memory addresses.
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LEA, // Load effective address to register.
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POPCNT, // Return count of bits set to 1 to register.
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BSF, // Bit scan forward on register or memory address.
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BSR, // Bit scan reverse on register or memory address.
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FADD, // Add literal or FPU stack with st0.
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FMUL, // Multiply literal or FPU stack with st0.
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FCOM, // Cmopare literal or FPU stack with st0.
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FCOMP, // Cmopare literal or FPU stack with st0 and pop.
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FSUB, // Subtract literal or FPU stack with st0.
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FSUBR, // Subtract reverse literal or FPU stack with st0.
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FDIV, // Divide literal or FPU stack with st0.
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FDIVR // Divide reverse literal or FPU stack with st0.
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ENTER,
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CALL,
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IN,
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OUT,
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JMP,
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JO,
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JNO,
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JB,
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JAE,
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JE,
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JNE,
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JBE,
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JA,
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JS,
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JNS,
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JPE,
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JPO,
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JL,
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JGE,
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JLE,
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JG,
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MOV,
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CMOVO,
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CMOVNO,
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CMOVB,
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CMOVAE,
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CMOVE,
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CMOVNE,
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CMOVBE,
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CMOVA,
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CMOVS,
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CMOVNS,
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CMOVPE,
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CMOVPO,
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CMOVL,
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CMOVGE,
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CMOVLE,
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CMOVG,
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PUSH,
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POP,
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BSWAP,
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TEST,
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RCL,
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RCR,
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ROL,
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ROR,
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SHL,
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SHR,
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SAL,
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SAR,
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REP,
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REPE,
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REPNE,
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REPZ,
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REPNZ,
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LOOP,
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LOOPE,
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LOOPNE,
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MOVBE,
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XADD,
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XCHG,
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LEA,
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POPCNT,
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BSF,
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BSR,
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FADD,
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FMUL,
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FCOM,
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FCOMP,
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FSUB,
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FSUBR,
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FDIV,
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FDIVR
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};
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enum {
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GR0, // Register: rax, eax, ax, al;
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GR1, // Register: rcx, ecx, cx, cl;
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GR2, // Register: rdx, edx, dx, dl;
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GR3, // Register: rbx, ebx, bx, bl;
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GR4, // Register: rsp, esp, sp, spl;
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GR5, // Register: rbp, ebp, bp, bpl;
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GR6, // Register: rsi, esi, si, sil;
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GR7, // Register: rdi, edi, di, dil;
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GR8, // Register: r8, r8d, r8w, r8b;
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GR9, // Register: r9, r9d, r9w, r9b;
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GR10, // Register: r10, r10d, r10w, r10b;
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GR11, // Register: r11, r11d, r11w, r11b;
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GR12, // Register: r12, r12d, r12w, r12b;
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GR13, // Register: r13, r13d, r13w, r13b;
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GR14, // Register: r14, r14d, r14w, r14b;
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GR15 // Register: r15, r15d, r15w, r15b;
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GR0,
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GR1,
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GR2,
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GR3,
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GR4,
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GR5,
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GR6,
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GR7,
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GR8,
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GR9,
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GR10,
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GR11,
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GR12,
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GR13,
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GR14,
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GR15
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};
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extern unsigned int text_entry_point;
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@ -155,34 +155,118 @@ nop { return INOP; }
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adc { return ITADC; }
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add { return ITADD; }
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and { return ITAND; }
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cbw { return ITCBW; }
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cdq { return ITCDQ; }
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cdqe { return ITCDQE; }
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clc { return ITCLC; }
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cld { return ITCLD; }
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cli { return ITCLI; }
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clts { return ITCLTS; }
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cmc { return ITCMC; }
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cmp { return ITCMP; }
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cpuid { return ITCPUID; }
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cqo { return ITCQO; }
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cwd { return ITCWD; }
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cwde { return ITCWDE; }
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dec { return ITDEC; }
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div { return ITDIV; }
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emms { return ITEMMS; }
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f2xm1 { return ITF2XM1; }
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fabs { return ITFABS; }
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fchs { return ITFCHS; }
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fcos { return ITFCOS; }
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fdecstp { return ITFDECSTP; }
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fincstp { return ITFINCSTP; }
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fld1 { return ITFLD1; }
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fldl2e { return ITFLDL2E; }
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fldl2t { return ITFLDL2T; }
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fldlg2 { return ITFLDLG2; }
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fldln2 { return ITFLDLN2; }
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fldpi { return ITFLDPI; }
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fldz { return ITFLDZ; }
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fnop { return ITFNOP; }
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fpatan { return ITFPATAN; }
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fprem { return ITFPREM; }
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fprem1 { return ITFPREM1; }
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fptan { return ITFPTAN; }
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frndint { return ITFRNDINT; }
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fscale { return ITFSCALE; }
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fsin { return ITFSIN; }
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fsincos { return ITFSINCOS; }
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fsqrt { return ITFSQRT; }
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ftst { return ITFTST; }
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fxam { return ITFXAM; }
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fxtract { return ITFXTRACT; }
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fyl2x { return ITFYL2X; }
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fyl2xp1 { return ITFYL2XP1; }
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hlt { return ITHLT; }
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idiv { return ITIDIV; }
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imul { return ITIMUL; }
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inal { return ITINAL; }
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inax { return ITINAX; }
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inc { return ITINC; }
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ineax { return ITINEAX; }
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insb { return ITINSB; }
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insd { return ITINSD; }
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insw { return ITINSW; }
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int3 { return ITINT3; }
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invd { return ITINVD; }
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iretd { return ITIRETD; }
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iretq { return ITIRETQ; }
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je { return ITJE; }
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jmp { return ITJMP; }
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jne { return ITJNE; }
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leave { return ITLEAVE; }
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lock { return ITLOCK; }
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lodsb { return ITLODSB; }
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lodsd { return ITLODSD; }
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lodsq { return ITLODSQ; }
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lodsw { return ITLODSW; }
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mov { return ITMOV; }
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mul { return ITMUL; }
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neg { return ITNEG; }
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nop { return ITNOP; }
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not { return ITNOT; }
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or { return ITOR; }
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outal { return ITOUTAL; }
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outax { return ITOUTAX; }
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outeax { return ITOUTEAX; }
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outsb { return ITOUTSB; }
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outsd { return ITOUTSD; }
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outsw { return ITOUTSW; }
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pause { return ITPAUSE; }
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pop { return ITPOP; }
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popf { return ITPOPF; }
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pushf { return ITPUSHF; }
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rdmsr { return ITRDMSR; }
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rdpmc { return ITRDPMC; }
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rdtsc { return ITRDTSC; }
|
||||
retf { return ITRETF; }
|
||||
retn { return ITRETN; }
|
||||
rsm { return ITRSM; }
|
||||
sar { return ITSAR; }
|
||||
sbb { return ITSBB; }
|
||||
scasb { return ITSCASB; }
|
||||
scasd { return ITSCASD; }
|
||||
scasq { return ITSCASQ; }
|
||||
scasw { return ITSCASW; }
|
||||
stc { return ITSTC; }
|
||||
std { return ITSTD; }
|
||||
sti { return ITSTI; }
|
||||
stosb { return ITSTOSB; }
|
||||
stosd { return ITSTOSD; }
|
||||
stosq { return ITSTOSQ; }
|
||||
stosw { return ITSTOSW; }
|
||||
sub { return ITSUB; }
|
||||
syscall { return ITSYSCALL; }
|
||||
sysenter { return ITSYSENTER; }
|
||||
sysexit { return ITSYSEXIT; }
|
||||
sysret { return ITSYSRET; }
|
||||
ud2 { return ITUD2; }
|
||||
wait { return ITWAIT; }
|
||||
wbinvd { return ITWBINVD; }
|
||||
wrmsr { return ITWRMSR; }
|
||||
xlatb { return ITXLATB; }
|
||||
xor { return ITXOR; }
|
||||
|
||||
/* #placeholder<instruction_scanner_instructions> END
|
||||
|
||||
100
source/eaxhla.y
100
source/eaxhla.y
@ -93,7 +93,7 @@
|
||||
// Instructions
|
||||
%token INOP
|
||||
// #placeholder<instruction_token_list> BEGIN
|
||||
%token ITADC ITADD ITAND ITCMP ITDEC ITDIV ITHLT ITIDIV ITIMUL ITINC ITJE ITJMP ITJNE ITLEAVE ITLOCK ITMOV ITMUL ITNEG ITNOT ITOR ITPAUSE ITPOP ITRETF ITRETN ITSAR ITSBB ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITXOR
|
||||
%token ITADC ITADD ITAND ITCBW ITCDQ ITCDQE ITCLC ITCLD ITCLI ITCLTS ITCMC ITCMP ITCPUID ITCQO ITCWD ITCWDE ITDEC ITDIV ITEMMS ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITHLT ITIDIV ITIMUL ITINAL ITINAX ITINC ITINEAX ITINSB ITINSD ITINSW ITINT3 ITINVD ITIRETD ITIRETQ ITJE ITJMP ITJNE ITLEAVE ITLOCK ITLODSB ITLODSD ITLODSQ ITLODSW ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITOUTAL ITOUTAX ITOUTEAX ITOUTSB ITOUTSD ITOUTSW ITPAUSE ITPOP ITPOPF ITPUSHF ITRDMSR ITRDPMC ITRDTSC ITRETF ITRETN ITRSM ITSAR ITSBB ITSCASB ITSCASD ITSCASQ ITSCASW ITSTC ITSTD ITSTI ITSTOSB ITSTOSD ITSTOSQ ITSTOSW ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITUD2 ITWAIT ITWBINVD ITWRMSR ITXLATB ITXOR
|
||||
// #placeholder<instruction_token_list> END
|
||||
|
||||
// Instruction-likes
|
||||
@ -423,16 +423,100 @@ library_code: %empty
|
||||
|
||||
instruction: INOP { append_instructions(NOP); }
|
||||
// #placeholder<instruction_parser_rules> BEGIN
|
||||
| ITNOP { append_instructions(NOP); }
|
||||
| ITRETN { append_instructions(RETN); }
|
||||
| ITRETF { append_instructions(RETF); }
|
||||
| ITLEAVE { append_instructions(LEAVE); }
|
||||
| ITLOCK { append_instructions(LOCK); }
|
||||
| ITHLT { append_instructions(HLT); }
|
||||
| ITPOPF { append_instructions(POPF); }
|
||||
| ITPUSHF { append_instructions(PUSHF); }
|
||||
| ITWAIT { append_instructions(WAIT); }
|
||||
| ITCLC { append_instructions(CLC); }
|
||||
| ITCLD { append_instructions(CLD); }
|
||||
| ITCLI { append_instructions(CLI); }
|
||||
| ITSTC { append_instructions(STC); }
|
||||
| ITSTD { append_instructions(STD); }
|
||||
| ITSTI { append_instructions(STI); }
|
||||
| ITCMC { append_instructions(CMC); }
|
||||
| ITINSB { append_instructions(INSB); }
|
||||
| ITINSD { append_instructions(INSD); }
|
||||
| ITOUTSB { append_instructions(OUTSB); }
|
||||
| ITOUTSD { append_instructions(OUTSD); }
|
||||
| ITCDQ { append_instructions(CDQ); }
|
||||
| ITCWDE { append_instructions(CWDE); }
|
||||
| ITINAL { append_instructions(INAL); }
|
||||
| ITINEAX { append_instructions(INEAX); }
|
||||
| ITINT3 { append_instructions(INT3); }
|
||||
| ITIRETD { append_instructions(IRETD); }
|
||||
| ITLODSB { append_instructions(LODSB); }
|
||||
| ITLODSD { append_instructions(LODSD); }
|
||||
| ITOUTAL { append_instructions(OUTAL); }
|
||||
| ITOUTEAX { append_instructions(OUTEAX); }
|
||||
| ITSCASB { append_instructions(SCASB); }
|
||||
| ITSCASD { append_instructions(SCASD); }
|
||||
| ITSTOSB { append_instructions(STOSB); }
|
||||
| ITSTOSD { append_instructions(STOSD); }
|
||||
| ITSYSENTER { append_instructions(SYSENTER); }
|
||||
| ITSYSEXIT { append_instructions(SYSEXIT); }
|
||||
| ITSYSCALL { append_instructions(SYSCALL); }
|
||||
| ITSYSRET { append_instructions(SYSRET); }
|
||||
| ITSYSEXIT { append_instructions(SYSEXIT); }
|
||||
| ITSYSENTER { append_instructions(SYSENTER); }
|
||||
| ITLEAVE { append_instructions(LEAVE); }
|
||||
| ITRETF { append_instructions(RETF); }
|
||||
| ITRETN { append_instructions(RETN); }
|
||||
| ITPAUSE { append_instructions(PAUSE); }
|
||||
| ITHLT { append_instructions(HLT); }
|
||||
| ITLOCK { append_instructions(LOCK); }
|
||||
| ITCPUID { append_instructions(CPUID); }
|
||||
| ITEMMS { append_instructions(EMMS); }
|
||||
| ITRSM { append_instructions(RSM); }
|
||||
| ITFNOP { append_instructions(FNOP); }
|
||||
| ITFCHS { append_instructions(FCHS); }
|
||||
| ITFABS { append_instructions(FABS); }
|
||||
| ITFTST { append_instructions(FTST); }
|
||||
| ITFXAM { append_instructions(FXAM); }
|
||||
| ITFLD1 { append_instructions(FLD1); }
|
||||
| ITFLDL2T { append_instructions(FLDL2T); }
|
||||
| ITFLDL2E { append_instructions(FLDL2E); }
|
||||
| ITFLDPI { append_instructions(FLDPI); }
|
||||
| ITFLDLG2 { append_instructions(FLDLG2); }
|
||||
| ITFLDLN2 { append_instructions(FLDLN2); }
|
||||
| ITFLDZ { append_instructions(FLDZ); }
|
||||
| ITF2XM1 { append_instructions(F2XM1); }
|
||||
| ITFYL2X { append_instructions(FYL2X); }
|
||||
| ITFPTAN { append_instructions(FPTAN); }
|
||||
| ITFPATAN { append_instructions(FPATAN); }
|
||||
| ITFXTRACT { append_instructions(FXTRACT); }
|
||||
| ITFPREM1 { append_instructions(FPREM1); }
|
||||
| ITFDECSTP { append_instructions(FDECSTP); }
|
||||
| ITFINCSTP { append_instructions(FINCSTP); }
|
||||
| ITFPREM { append_instructions(FPREM); }
|
||||
| ITFYL2XP1 { append_instructions(FYL2XP1); }
|
||||
| ITFSQRT { append_instructions(FSQRT); }
|
||||
| ITFSINCOS { append_instructions(FSINCOS); }
|
||||
| ITFRNDINT { append_instructions(FRNDINT); }
|
||||
| ITFSCALE { append_instructions(FSCALE); }
|
||||
| ITFSIN { append_instructions(FSIN); }
|
||||
| ITFCOS { append_instructions(FCOS); }
|
||||
| ITINSW { append_instructions(INSW); }
|
||||
| ITOUTSW { append_instructions(OUTSW); }
|
||||
| ITCWD { append_instructions(CWD); }
|
||||
| ITCQO { append_instructions(CQO); }
|
||||
| ITCBW { append_instructions(CBW); }
|
||||
| ITCDQE { append_instructions(CDQE); }
|
||||
| ITINVD { append_instructions(INVD); }
|
||||
| ITWBINVD { append_instructions(WBINVD); }
|
||||
| ITUD2 { append_instructions(UD2); }
|
||||
| ITCLTS { append_instructions(CLTS); }
|
||||
| ITINAX { append_instructions(INAX); }
|
||||
| ITIRETQ { append_instructions(IRETQ); }
|
||||
| ITLODSW { append_instructions(LODSW); }
|
||||
| ITLODSQ { append_instructions(LODSQ); }
|
||||
| ITOUTAX { append_instructions(OUTAX); }
|
||||
| ITRDPMC { append_instructions(RDPMC); }
|
||||
| ITRDMSR { append_instructions(RDMSR); }
|
||||
| ITRDTSC { append_instructions(RDTSC); }
|
||||
| ITSCASW { append_instructions(SCASW); }
|
||||
| ITSCASQ { append_instructions(SCASQ); }
|
||||
| ITSTOSW { append_instructions(STOSW); }
|
||||
| ITSTOSQ { append_instructions(STOSQ); }
|
||||
| ITWRMSR { append_instructions(WRMSR); }
|
||||
| ITXLATB { append_instructions(XLATB); }
|
||||
| ITJMP relative { append_instructions( JMP, D32, REL, $2 ); }
|
||||
| ITJE relative { append_instructions( JE, D32, REL, $2 ); }
|
||||
| ITJNE relative { append_instructions( JNE, D32, REL, $2 ); }
|
||||
|
||||
@ -1,14 +1,98 @@
|
||||
set instructions {
|
||||
{nop}
|
||||
{retn}
|
||||
{retf}
|
||||
{leave}
|
||||
{lock}
|
||||
{hlt}
|
||||
{popf}
|
||||
{pushf}
|
||||
{wait}
|
||||
{clc}
|
||||
{cld}
|
||||
{cli}
|
||||
{stc}
|
||||
{std}
|
||||
{sti}
|
||||
{cmc}
|
||||
{insb}
|
||||
{insd}
|
||||
{outsb}
|
||||
{outsd}
|
||||
{cdq}
|
||||
{cwde}
|
||||
{inal}
|
||||
{ineax}
|
||||
{int3}
|
||||
{iretd}
|
||||
{lodsb}
|
||||
{lodsd}
|
||||
{outal}
|
||||
{outeax}
|
||||
{scasb}
|
||||
{scasd}
|
||||
{stosb}
|
||||
{stosd}
|
||||
{sysenter}
|
||||
{sysexit}
|
||||
{syscall}
|
||||
{sysret}
|
||||
{sysexit}
|
||||
{sysenter}
|
||||
{leave}
|
||||
{retf}
|
||||
{retn}
|
||||
{pause}
|
||||
{hlt}
|
||||
{lock}
|
||||
{cpuid}
|
||||
{emms}
|
||||
{rsm}
|
||||
{fnop}
|
||||
{fchs}
|
||||
{fabs}
|
||||
{ftst}
|
||||
{fxam}
|
||||
{fld1}
|
||||
{fldl2t}
|
||||
{fldl2e}
|
||||
{fldpi}
|
||||
{fldlg2}
|
||||
{fldln2}
|
||||
{fldz}
|
||||
{f2xm1}
|
||||
{fyl2x}
|
||||
{fptan}
|
||||
{fpatan}
|
||||
{fxtract}
|
||||
{fprem1}
|
||||
{fdecstp}
|
||||
{fincstp}
|
||||
{fprem}
|
||||
{fyl2xp1}
|
||||
{fsqrt}
|
||||
{fsincos}
|
||||
{frndint}
|
||||
{fscale}
|
||||
{fsin}
|
||||
{fcos}
|
||||
{insw}
|
||||
{outsw}
|
||||
{cwd}
|
||||
{cqo}
|
||||
{cbw}
|
||||
{cdqe}
|
||||
{invd}
|
||||
{wbinvd}
|
||||
{ud2}
|
||||
{clts}
|
||||
{inax}
|
||||
{iretq}
|
||||
{lodsw}
|
||||
{lodsq}
|
||||
{outax}
|
||||
{rdpmc}
|
||||
{rdmsr}
|
||||
{rdtsc}
|
||||
{scasw}
|
||||
{scasq}
|
||||
{stosw}
|
||||
{stosq}
|
||||
{wrmsr}
|
||||
{xlatb}
|
||||
{jmp relative}
|
||||
{je relative}
|
||||
{jne relative}
|
||||
@ -45,7 +129,7 @@ set instructions {
|
||||
{mov memory register}
|
||||
{sar register immediate}
|
||||
}
|
||||
|
||||
|
||||
proc malformed_instruction {i} {
|
||||
error [format "Instruction {%s} is malformed" [join $i ", "]]
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user