560 lines
18 KiB
Plaintext
560 lines
18 KiB
Plaintext
/* EAXHLA parser
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* This source file has minimal knowledge about highlevel constructs.
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* The only time it interacts with the assembler interface directly is when
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* instructions are encountered or processing a machine code block,
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* everything else is delegated to eaxhla.c
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*/
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%code requires {
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#include "eaxhla.h"
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}
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%{
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#include <stdio.h>
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#include <math.h>
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#include <stdbool.h>
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#include "eaxhla.h"
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#include "eaxhla.yy.h"
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#include "assembler.h"
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#include "compile.h"
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#include "debug.h"
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extern void yyfree_leftovers(void);
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extern char * yyfilename;
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void yyerror(const char * errmsg) {
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issue_error("%s near \033[1m'%s'\033[0m", errmsg, yytext);
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}
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%}
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%union{
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long intval;
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char * strval;
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struct {
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int type;
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int value;
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} argval;
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struct {
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unsigned long long len;
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void * data;
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} blobval;
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symbol_t varval;
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cpuregister_t regval;
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}
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%token MYBEGIN
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%token PROGRAM END_PROGRAM
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%token PROCEDURE END_PROCEDURE
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%token REPEAT END_REPEAT
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%token IF THEN ELSE END_IF
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%token MACHINE END_MACHINE
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%token LIBRARY END_LIBRARY
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%token UNTIL
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%token<strval> IDENTIFIER LABEL
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%type<argval> immediate
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%type<intval> memory dereference relative
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%type<intval> artimetric_block artimetric_expression artimetric_operand
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%type<intval> value
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%token<intval> LITERAL
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%token<blobval> ARRAY_LITERAL
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// Specifiers
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%token FAST
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%token UNIX WIN64
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// Logic
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%token ITNEQ
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/*
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%token ITOR ITXOR ITAND ITNOT // these are (in)conveniently instructions too
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*/
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// Type info
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%token TIN
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%token S8 S16 S32 S64
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%token U8 U16 U32 U64
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%type<intval> type
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%type<varval> declaration
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%type<varval> stored_literal
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// Registers
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%type<regval> register register64s register32s register16s register8s
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// #placeholder<register_token_list> BEGIN
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%token RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15
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%token EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D
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%token AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W
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%token AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B
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// #placeholder<register_token_list> END
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// Instructions
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%token INOP
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// #placeholder<instruction_token_list> BEGIN
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%token ITADC ITADD ITAND ITCBW ITCDQ ITCDQE ITCLC ITCLD ITCLI ITCLTS ITCMC ITCMP ITCPUID ITCQO ITCWD ITCWDE ITDEC ITDIV ITEMMS ITF2XM1 ITFABS ITFCHS ITFCOS ITFDECSTP ITFINCSTP ITFLD1 ITFLDL2E ITFLDL2T ITFLDLG2 ITFLDLN2 ITFLDPI ITFLDZ ITFNOP ITFPATAN ITFPREM ITFPREM1 ITFPTAN ITFRNDINT ITFSCALE ITFSIN ITFSINCOS ITFSQRT ITFTST ITFXAM ITFXTRACT ITFYL2X ITFYL2XP1 ITHLT ITIDIV ITIMUL ITINAL ITINAX ITINC ITINEAX ITINSB ITINSD ITINSW ITINT3 ITINVD ITIRETD ITIRETQ ITJE ITJMP ITJNE ITLEAVE ITLOCK ITLODSB ITLODSD ITLODSQ ITLODSW ITMOV ITMUL ITNEG ITNOP ITNOT ITOR ITOUTAL ITOUTAX ITOUTEAX ITOUTSB ITOUTSD ITOUTSW ITPAUSE ITPOP ITPOPF ITPUSHF ITRDMSR ITRDPMC ITRDTSC ITRETF ITRETN ITRSM ITSAR ITSBB ITSCASB ITSCASD ITSCASQ ITSCASW ITSTC ITSTD ITSTI ITSTOSB ITSTOSD ITSTOSQ ITSTOSW ITSUB ITSYSCALL ITSYSENTER ITSYSEXIT ITSYSRET ITUD2 ITWAIT ITWBINVD ITWRMSR ITXLATB ITXOR
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// #placeholder<instruction_token_list> END
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// Instruction-likes
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%token FASTCALL
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%token EXIT BREAK
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%%
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document: hla { fin_hla(); }
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;
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hla: %empty
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// | library hla
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| declaration hla // tmp
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| program hla
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| function hla
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;
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program: program_head declaration_section MYBEGIN code END_PROGRAM {
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}
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;
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program_head: program_specifier PROGRAM IDENTIFIER {
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add_scope($3);
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add_program($3);
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free($3);
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};
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program_specifier: %empty
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| system_specifier
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;
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system_specifier: UNIX { system_type = UNIX; }
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| WIN64 { system_type = WIN64; }
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;
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// XXX: end procedure thing
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function: function_head declaration_section MYBEGIN code END_PROCEDURE {
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fin_procedure();
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}
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;
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function_head: function_specifier PROCEDURE IDENTIFIER {
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add_scope($3);
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add_procedure($3);
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free($3);
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}
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;
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function_specifier: %empty
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| FAST
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;
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declaration_section: %empty
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| declaration declaration_section
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| error declaration_section { yyerrok; }
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;
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declaration:
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variable_specifier type IDENTIFIER {
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add_variable($2, $3);
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free($3);
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}
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| variable_specifier type IDENTIFIER '=' LITERAL {
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add_variable_with_value($2, $3, $5);
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free($3);
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}
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| variable_specifier type '<' value '>' IDENTIFIER {
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add_array_variable($2, $6, $4);
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free($6);
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}
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| variable_specifier type '<' value '>' IDENTIFIER '=' ARRAY_LITERAL {
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add_array_variable_with_value($2, $6, $4, $8.data, $8.len);
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free($6);
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}
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| variable_specifier type '<' '>' IDENTIFIER '=' ARRAY_LITERAL {
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add_array_variable_with_value($2, $5, $7.len, $7.data, $7.len);
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free($5);
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}
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;
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variable_specifier: %empty
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| TIN
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;
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type: S8 { $$ = S8; }
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| S16 { $$ = S16; }
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| S32 { $$ = S32; }
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| S64 { $$ = S64; }
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| U8 { $$ = U8; }
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| U16 { $$ = U16; }
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| U32 { $$ = U32; }
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| U64 { $$ = U64; }
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;
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immediate: LITERAL {
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$$.type = IMM;
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$$.value = $1;
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}
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| IDENTIFIER {
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symbol_t * variable = get_variable($1);
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$$.type = REL;
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$$.value = variable->_id;
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free($1);
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}
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;
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memory: artimetric_block
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| dereference
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;
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dereference: '[' IDENTIFIER ']' {
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$$ = get_variable($2)->_id;
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free($2);
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}
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| '[' IDENTIFIER '+' value ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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| '[' IDENTIFIER '-' value ']' { $$ = 0; /* XXX: how the fuck do i dereference? */ }
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;
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relative: IDENTIFIER {
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$$ = get_relative($1)->_id;
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free($1);
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}
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;
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value: artimetric_block
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| LITERAL
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| IDENTIFIER {
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symbol_t * var = get_variable($1);
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$$ = var->value;
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free($1);
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}
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;
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stored_literal: ARRAY_LITERAL {
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add_literal($1.data, $1.len);
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}
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;
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code: %empty
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| error code { /*yyerrok;*/ }
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| repeat code
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| if code
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| call code
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| label code
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| machine code
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| BREAK code
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| exit code
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| instruction code
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;
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label: LABEL {
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add_label($1, true);
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free($1);
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}
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;
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repeat: REPEAT code END_REPEAT
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| UNTIL logic REPEAT code END_REPEAT
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;
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if: IF logic THEN code END_IF
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| IF logic THEN code ELSE code END_IF
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;
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logic: logical_operand ITAND logical_operand
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| logical_operand ITOR logical_operand
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| logical_operand ITXOR logical_operand
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| logical_operand '=' logical_operand
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| logical_operand ITNEQ logical_operand
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| sublogic
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| ITNOT logic
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;
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logical_operand: sublogic
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| register
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| artimetric_block
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| dereference
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| LITERAL
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| IDENTIFIER
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;
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sublogic: '(' logic ')'
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;
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machine: MACHINE machine_code END_MACHINE
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;
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machine_code: %empty
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| machine_code LITERAL {
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append_instructions(ASMDIRIMM, D8, 1, $2);
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}
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| machine_code ARRAY_LITERAL {
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append_instructions(ASMDIRIMM, D8, $2.len);
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for (unsigned long long i = 0; i < $2.len; i++) {
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append_instructions(((char*)$2.data)[i]);
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}
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}
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| machine_code IDENTIFIER { free($2); }
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;
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call: FASTCALL IDENTIFIER arguments {
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add_fastcall($2);
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free($2);
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}
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;
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arguments: %empty
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| IDENTIFIER arguments { free($1); }
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| LITERAL arguments
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| register arguments
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| artimetric_block arguments
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| stored_literal arguments
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;
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register: register64s { $$ = $1; $$.size = D64; }
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| register32s { $$ = $1; $$.size = D32; }
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| register16s { $$ = $1; $$.size = D16; }
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| register8s { $$ = $1; $$.size = D8; }
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;
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// #placeholder<register_parser_rules> BEGIN
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register64s: RAX { $$.number = GR0; }
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| RCX { $$.number = GR1; }
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| RDX { $$.number = GR2; }
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| RBX { $$.number = GR3; }
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| RSP { $$.number = GR4; }
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| RBP { $$.number = GR5; }
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| RSI { $$.number = GR6; }
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| RDI { $$.number = GR7; }
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| R8 { $$.number = GR8; }
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| R9 { $$.number = GR9; }
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| R10 { $$.number = GR10; }
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| R11 { $$.number = GR11; }
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| R12 { $$.number = GR12; }
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| R13 { $$.number = GR13; }
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| R14 { $$.number = GR14; }
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| R15 { $$.number = GR15; }
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;
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register32s: EAX { $$.number = GR0; }
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| ECX { $$.number = GR1; }
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| EDX { $$.number = GR2; }
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| EBX { $$.number = GR3; }
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| ESP { $$.number = GR4; }
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| EBP { $$.number = GR5; }
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| ESI { $$.number = GR6; }
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| EDI { $$.number = GR7; }
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| R8D { $$.number = GR8; }
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| R9D { $$.number = GR9; }
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| R10D { $$.number = GR10; }
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| R11D { $$.number = GR11; }
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| R12D { $$.number = GR12; }
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| R13D { $$.number = GR13; }
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| R14D { $$.number = GR14; }
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| R15D { $$.number = GR15; }
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;
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register16s: AX { $$.number = GR0; }
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| CX { $$.number = GR1; }
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| DX { $$.number = GR2; }
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| BX { $$.number = GR3; }
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| SP { $$.number = GR4; }
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| BP { $$.number = GR5; }
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| SI { $$.number = GR6; }
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| DI { $$.number = GR7; }
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| R8W { $$.number = GR8; }
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| R9W { $$.number = GR9; }
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| R10W { $$.number = GR10; }
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| R11W { $$.number = GR11; }
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| R12W { $$.number = GR12; }
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| R13W { $$.number = GR13; }
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| R14W { $$.number = GR14; }
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| R15W { $$.number = GR15; }
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;
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register8s: AL { $$.number = GR0; }
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| CL { $$.number = GR1; }
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| DL { $$.number = GR2; }
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| BL { $$.number = GR3; }
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| SPL { $$.number = GR4; }
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| BPL { $$.number = GR5; }
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| SIL { $$.number = GR6; }
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| DIL { $$.number = GR7; }
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| R8B { $$.number = GR8; }
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| R9B { $$.number = GR9; }
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| R10B { $$.number = GR10; }
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| R11B { $$.number = GR11; }
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| R12B { $$.number = GR12; }
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| R13B { $$.number = GR13; }
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| R14B { $$.number = GR14; }
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| R15B { $$.number = GR15; }
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;
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// #placeholder<register_parser_rules> END
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artimetric_block: '{' artimetric_expression '}' { $$ = $2; }
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;
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artimetric_expression: %empty { $$ = 0; }
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| artimetric_operand
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| artimetric_expression '+' artimetric_operand { $$ = $1 + $3; }
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| artimetric_expression '-' artimetric_operand { $$ = $1 - $3; }
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| artimetric_expression '*' artimetric_operand { $$ = $1 * $3; }
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| artimetric_expression '/' artimetric_operand { $$ = $1 / $3; }
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| artimetric_expression '%' artimetric_operand { $$ = $1 % $3; }
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| artimetric_expression '^' artimetric_operand { $$ = pow($1, $3); }
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;
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artimetric_operand: LITERAL
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| IDENTIFIER {
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$$ = get_variable($1)->value;
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}
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;
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exit: EXIT value { append_exit($2); }
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;
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/* XXX
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library: LIBRARY declaration_section MYBEGIN library_code END_LIBRARY
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;
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library_code: %empty
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| function library_code
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;
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*/
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instruction: INOP { append_instructions(NOP); }
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// #placeholder<instruction_parser_rules> BEGIN
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| ITNOP { append_instructions(NOP); }
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| ITRETN { append_instructions(RETN); }
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| ITRETF { append_instructions(RETF); }
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| ITLEAVE { append_instructions(LEAVE); }
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| ITLOCK { append_instructions(LOCK); }
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| ITHLT { append_instructions(HLT); }
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| ITPOPF { append_instructions(POPF); }
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| ITPUSHF { append_instructions(PUSHF); }
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| ITWAIT { append_instructions(WAIT); }
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| ITCLC { append_instructions(CLC); }
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| ITCLD { append_instructions(CLD); }
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| ITCLI { append_instructions(CLI); }
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| ITSTC { append_instructions(STC); }
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| ITSTD { append_instructions(STD); }
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| ITSTI { append_instructions(STI); }
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| ITCMC { append_instructions(CMC); }
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| ITINSB { append_instructions(INSB); }
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| ITINSD { append_instructions(INSD); }
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| ITOUTSB { append_instructions(OUTSB); }
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| ITOUTSD { append_instructions(OUTSD); }
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| ITCDQ { append_instructions(CDQ); }
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| ITCWDE { append_instructions(CWDE); }
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| ITINAL { append_instructions(INAL); }
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| ITINEAX { append_instructions(INEAX); }
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| ITINT3 { append_instructions(INT3); }
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| ITIRETD { append_instructions(IRETD); }
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| ITLODSB { append_instructions(LODSB); }
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| ITLODSD { append_instructions(LODSD); }
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| ITOUTAL { append_instructions(OUTAL); }
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| ITOUTEAX { append_instructions(OUTEAX); }
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| ITSCASB { append_instructions(SCASB); }
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| ITSCASD { append_instructions(SCASD); }
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| ITSTOSB { append_instructions(STOSB); }
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| ITSTOSD { append_instructions(STOSD); }
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| ITSYSENTER { append_instructions(SYSENTER); }
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| ITSYSEXIT { append_instructions(SYSEXIT); }
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| ITSYSCALL { append_instructions(SYSCALL); }
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| ITSYSRET { append_instructions(SYSRET); }
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| ITPAUSE { append_instructions(PAUSE); }
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| ITCPUID { append_instructions(CPUID); }
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| ITEMMS { append_instructions(EMMS); }
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| ITRSM { append_instructions(RSM); }
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| ITFNOP { append_instructions(FNOP); }
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| ITFCHS { append_instructions(FCHS); }
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| ITFABS { append_instructions(FABS); }
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| ITFTST { append_instructions(FTST); }
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| ITFXAM { append_instructions(FXAM); }
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| ITFLD1 { append_instructions(FLD1); }
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| ITFLDL2T { append_instructions(FLDL2T); }
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| ITFLDL2E { append_instructions(FLDL2E); }
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| ITFLDPI { append_instructions(FLDPI); }
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| ITFLDLG2 { append_instructions(FLDLG2); }
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| ITFLDLN2 { append_instructions(FLDLN2); }
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| ITFLDZ { append_instructions(FLDZ); }
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| ITF2XM1 { append_instructions(F2XM1); }
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| ITFYL2X { append_instructions(FYL2X); }
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| ITFPTAN { append_instructions(FPTAN); }
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| ITFPATAN { append_instructions(FPATAN); }
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| ITFXTRACT { append_instructions(FXTRACT); }
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| ITFPREM1 { append_instructions(FPREM1); }
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| ITFDECSTP { append_instructions(FDECSTP); }
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| ITFINCSTP { append_instructions(FINCSTP); }
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|
| ITFPREM { append_instructions(FPREM); }
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|
| ITFYL2XP1 { append_instructions(FYL2XP1); }
|
|
| ITFSQRT { append_instructions(FSQRT); }
|
|
| ITFSINCOS { append_instructions(FSINCOS); }
|
|
| ITFRNDINT { append_instructions(FRNDINT); }
|
|
| ITFSCALE { append_instructions(FSCALE); }
|
|
| ITFSIN { append_instructions(FSIN); }
|
|
| ITFCOS { append_instructions(FCOS); }
|
|
| ITINSW { append_instructions(INSW); }
|
|
| ITOUTSW { append_instructions(OUTSW); }
|
|
| ITCWD { append_instructions(CWD); }
|
|
| ITCQO { append_instructions(CQO); }
|
|
| ITCBW { append_instructions(CBW); }
|
|
| ITCDQE { append_instructions(CDQE); }
|
|
| ITINVD { append_instructions(INVD); }
|
|
| ITWBINVD { append_instructions(WBINVD); }
|
|
| ITUD2 { append_instructions(UD2); }
|
|
| ITCLTS { append_instructions(CLTS); }
|
|
| ITINAX { append_instructions(INAX); }
|
|
| ITIRETQ { append_instructions(IRETQ); }
|
|
| ITLODSW { append_instructions(LODSW); }
|
|
| ITLODSQ { append_instructions(LODSQ); }
|
|
| ITOUTAX { append_instructions(OUTAX); }
|
|
| ITRDPMC { append_instructions(RDPMC); }
|
|
| ITRDMSR { append_instructions(RDMSR); }
|
|
| ITRDTSC { append_instructions(RDTSC); }
|
|
| ITSCASW { append_instructions(SCASW); }
|
|
| ITSCASQ { append_instructions(SCASQ); }
|
|
| ITSTOSW { append_instructions(STOSW); }
|
|
| ITSTOSQ { append_instructions(STOSQ); }
|
|
| ITWRMSR { append_instructions(WRMSR); }
|
|
| ITXLATB { append_instructions(XLATB); }
|
|
| ITJMP relative { append_instructions( JMP, D32, REL, $2 ); }
|
|
| ITJE relative { append_instructions( JE, D32, REL, $2 ); }
|
|
| ITJNE relative { append_instructions( JNE, D32, REL, $2 ); }
|
|
| ITINC register { append_instructions( INC, $2.size, REG, $2.number ); }
|
|
| ITDEC register { append_instructions( DEC, $2.size, REG, $2.number ); }
|
|
| ITNOT register { append_instructions( NOT, $2.size, REG, $2.number ); }
|
|
| ITNEG register { append_instructions( NEG, $2.size, REG, $2.number ); }
|
|
| ITMUL register { append_instructions( MUL, $2.size, REG, $2.number ); }
|
|
| ITIMUL register { append_instructions( IMUL, $2.size, REG, $2.number ); }
|
|
| ITDIV register { append_instructions( DIV, $2.size, REG, $2.number ); }
|
|
| ITIDIV register { append_instructions( IDIV, $2.size, REG, $2.number ); }
|
|
| ITPOP register { append_instructions( POP, $2.size, REG, $2.number ); }
|
|
| ITINC memory { append_instructions( INC, D32, MEM, $2 ); }
|
|
| ITDEC memory { append_instructions( DEC, D32, MEM, $2 ); }
|
|
| ITNOT memory { append_instructions( NOT, D32, MEM, $2 ); }
|
|
| ITNEG memory { append_instructions( NEG, D32, MEM, $2 ); }
|
|
| ITMUL memory { append_instructions( MUL, D32, MEM, $2 ); }
|
|
| ITIMUL memory { append_instructions( IMUL, D32, MEM, $2 ); }
|
|
| ITDIV memory { append_instructions( DIV, D32, MEM, $2 ); }
|
|
| ITIDIV memory { append_instructions( IDIV, D32, MEM, $2 ); }
|
|
| ITADD register register { append_instructions( ADD, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITOR register register { append_instructions( OR, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITADC register register { append_instructions( ADC, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITSBB register register { append_instructions( SBB, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITAND register register { append_instructions( AND, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITAND register immediate { append_instructions( AND, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITSUB register register { append_instructions( SUB, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITXOR register register { append_instructions( XOR, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITCMP register register { append_instructions( CMP, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITCMP register immediate { append_instructions( CMP, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITMOV register register { append_instructions( MOV, $2.size, REG, $2.number, REG, $3.number ); }
|
|
| ITMOV register immediate { append_instructions( MOV, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
| ITMOV register memory { append_instructions( MOV, $2.size, REG, $2.number, MEM, $3 ); }
|
|
| ITMOV memory register { append_instructions( MOV, D32, MEM, $2, REG, $3.number ); }
|
|
| ITSAR register immediate { append_instructions( SAR, $2.size, REG, $2.number, $3.type, $3.value ); }
|
|
|
|
// #placeholder<instruction_parser_rules> END
|
|
;
|
|
|
|
%%
|